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author | Nate Begeman <natebegeman@mac.com> | 2007-11-27 19:28:48 +0000 |
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committer | Nate Begeman <natebegeman@mac.com> | 2007-11-27 19:28:48 +0000 |
commit | d73ab8884f5c95d2704be3c00af4cc3dba963da6 (patch) | |
tree | 476412a752708d1e7cc44f60bb2953d3650d557b | |
parent | 19914ed97ffc2a655628bf237e795703ad2c4476 (diff) | |
download | llvm-d73ab8884f5c95d2704be3c00af4cc3dba963da6.tar.gz llvm-d73ab8884f5c95d2704be3c00af4cc3dba963da6.tar.bz2 llvm-d73ab8884f5c95d2704be3c00af4cc3dba963da6.tar.xz |
Support returning non-power-of-2 vectors to unblock some work
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44371 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 7 | ||||
-rw-r--r-- | lib/Target/X86/X86CallingConv.td | 10 |
2 files changed, 13 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index eadfa1fbb2..2be31c8260 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -364,6 +364,13 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT, unsigned NumVectorRegs = 1; + // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we + // could break down into LHS/RHS like LegalizeDAG does. + if (!isPowerOf2_32(NumElts)) { + NumVectorRegs = NumElts; + NumElts = 1; + } + // Divide the input until we get to a supported size. This will always // end with a scalar if the target doesn't support vectors. while (NumElts > 1 && diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td index bb054e8f05..aacd5a401d 100644 --- a/lib/Target/X86/X86CallingConv.td +++ b/lib/Target/X86/X86CallingConv.td @@ -52,10 +52,12 @@ def RetCC_X86_32_C : CallingConv<[ // X86-32 FastCC return-value convention. def RetCC_X86_32_Fast : CallingConv<[ - // The X86-32 fastcc returns FP values in XMM0 if the target has SSE2, - // otherwise it is the the C calling conventions. - CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, - CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>, + // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has + // SSE2, otherwise it is the the C calling conventions. + // This can happen when a float, 2 x float, or 3 x float vector is split by + // target lowering, and is returned in 1-3 sse regs. + CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, + CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, CCDelegateTo<RetCC_X86Common> ]>; |