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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-02 23:36:01 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-02 23:36:01 +0000 |
commit | da15a0ed4cd74f767cc124b65b7b7d9482969318 (patch) | |
tree | f6e420b182b4e2dacdb3716ac59eb1092d67acb5 | |
parent | 78c796e20303a99641841a663865c3d9db4464f7 (diff) | |
download | llvm-da15a0ed4cd74f767cc124b65b7b7d9482969318.tar.gz llvm-da15a0ed4cd74f767cc124b65b7b7d9482969318.tar.bz2 llvm-da15a0ed4cd74f767cc124b65b7b7d9482969318.tar.xz |
[mips] Do not reserve all 64-bit registers, but only the ones which need to be
reserved. Without this fix, RegScavenger::getRegsAvailable incorrectly
returns an empty set of integer registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167335 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.cpp | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index dd1a42b03b..8917820251 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -94,20 +94,16 @@ getReservedRegs(const MachineFunction &MF) const { for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I) Reserved.set(ReservedCPURegs[I]); - if (Subtarget.hasMips64()) { - for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I) - Reserved.set(ReservedCPU64Regs[I]); + for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I) + Reserved.set(ReservedCPU64Regs[I]); + if (Subtarget.hasMips64()) { // Reserve all registers in AFGR64. for (RegIter Reg = Mips::AFGR64RegClass.begin(), EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) Reserved.set(*Reg); } else { - // Reserve all registers in CPU64Regs & FGR64. - for (RegIter Reg = Mips::CPU64RegsRegClass.begin(), - EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg) - Reserved.set(*Reg); - + // Reserve all registers in FGR64. for (RegIter Reg = Mips::FGR64RegClass.begin(), EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) Reserved.set(*Reg); |