Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.

Add the 16-bit lane variants while I'm at it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 135 insertions, 28 deletions

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 6940156c7b..84b4319b76 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -1999,23 +1999,23 @@ multiclass VFPDT8ReqInstAlias<string opc, string asm, dag Result> {
   def I8 : VFPDataTypeInstAlias<opc, ".i8", asm, Result>;
   def S8 : VFPDataTypeInstAlias<opc, ".s8", asm, Result>;
   def U8 : VFPDataTypeInstAlias<opc, ".u8", asm, Result>;
-  def F8 : VFPDataTypeInstAlias<opc, ".p8", asm, Result>;
+  def P8 : VFPDataTypeInstAlias<opc, ".p8", asm, Result>;
 }
 // VFPDT8ReqInstAlias plus plain ".8"
 multiclass VFPDT8InstAlias<string opc, string asm, dag Result> {
   def _8 : VFPDataTypeInstAlias<opc, ".8", asm, Result>;
-  defm : VFPDT8ReqInstAlias<opc, asm, Result>;
+  defm _ : VFPDT8ReqInstAlias<opc, asm, Result>;
 }
 multiclass VFPDT16ReqInstAlias<string opc, string asm, dag Result> {
   def I16 : VFPDataTypeInstAlias<opc, ".i16", asm, Result>;
   def S16 : VFPDataTypeInstAlias<opc, ".s16", asm, Result>;
   def U16 : VFPDataTypeInstAlias<opc, ".u16", asm, Result>;
-  def F16 : VFPDataTypeInstAlias<opc, ".p16", asm, Result>;
+  def P16 : VFPDataTypeInstAlias<opc, ".p16", asm, Result>;
 }
 // VFPDT16ReqInstAlias plus plain ".16"
 multiclass VFPDT16InstAlias<string opc, string asm, dag Result> {
   def _16 : VFPDataTypeInstAlias<opc, ".16", asm, Result>;
-  defm : VFPDT16ReqInstAlias<opc, asm, Result>;
+  defm _ : VFPDT16ReqInstAlias<opc, asm, Result>;
 }
 multiclass VFPDT32ReqInstAlias<string opc, string asm, dag Result> {
   def I32 : VFPDataTypeInstAlias<opc, ".i32", asm, Result>;
@@ -2027,7 +2027,7 @@ multiclass VFPDT32ReqInstAlias<string opc, string asm, dag Result> {
 // VFPDT32ReqInstAlias plus plain ".32"
 multiclass VFPDT32InstAlias<string opc, string asm, dag Result> {
   def _32 : VFPDataTypeInstAlias<opc, ".32", asm, Result>;
-  defm : VFPDT32ReqInstAlias<opc, asm, Result>;
+  defm _ : VFPDT32ReqInstAlias<opc, asm, Result>;
 }
 multiclass VFPDT64ReqInstAlias<string opc, string asm, dag Result> {
   def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
@@ -2039,7 +2039,7 @@ multiclass VFPDT64ReqInstAlias<string opc, string asm, dag Result> {
 // VFPDT64ReqInstAlias plus plain ".64"
 multiclass VFPDT64InstAlias<string opc, string asm, dag Result> {
   def _64 : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
-  defm : VFPDT64ReqInstAlias<opc, asm, Result>;
+  defm _ : VFPDT64ReqInstAlias<opc, asm, Result>;
 }
 multiclass VFPDT64NoF64ReqInstAlias<string opc, string asm, dag Result> {
   def I64 : VFPDataTypeInstAlias<opc, ".i64", asm, Result>;
@@ -2050,17 +2050,94 @@ multiclass VFPDT64NoF64ReqInstAlias<string opc, string asm, dag Result> {
 // VFPDT64ReqInstAlias plus plain ".64"
 multiclass VFPDT64NoF64InstAlias<string opc, string asm, dag Result> {
   def _64 : VFPDataTypeInstAlias<opc, ".64", asm, Result>;
-  defm : VFPDT64ReqInstAlias<opc, asm, Result>;
+  defm _ : VFPDT64ReqInstAlias<opc, asm, Result>;
 }
 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result> {
-  defm : VFPDT8InstAlias<opc, asm, Result>;
-  defm : VFPDT16InstAlias<opc, asm, Result>;
-  defm : VFPDT32InstAlias<opc, asm, Result>;
-  defm : VFPDT64InstAlias<opc, asm, Result>;
+  defm _ : VFPDT8InstAlias<opc, asm, Result>;
+  defm _ : VFPDT16InstAlias<opc, asm, Result>;
+  defm _ : VFPDT32InstAlias<opc, asm, Result>;
+  defm _ : VFPDT64InstAlias<opc, asm, Result>;
 }
 multiclass VFPDTAnyNoF64InstAlias<string opc, string asm, dag Result> {
-  defm : VFPDT8InstAlias<opc, asm, Result>;
-  defm : VFPDT16InstAlias<opc, asm, Result>;
-  defm : VFPDT32InstAlias<opc, asm, Result>;
-  defm : VFPDT64NoF64InstAlias<opc, asm, Result>;
+  defm _ : VFPDT8InstAlias<opc, asm, Result>;
+  defm _ : VFPDT16InstAlias<opc, asm, Result>;
+  defm _ : VFPDT32InstAlias<opc, asm, Result>;
+  defm _ : VFPDT64NoF64InstAlias<opc, asm, Result>;
+}
+
+// The same alias classes using AsmPseudo instead, for the more complex
+// stuff in NEON that InstAlias can't quite handle.
+// Note that we can't use anonymous defm references here like we can
+// above, as we care about the ultimate instruction enum names generated, unlike
+// for instalias defs.
+class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
+  AsmPseudoInst<!strconcat(opc, dt, asm), iops>, Requires<[HasNEON]>;
+multiclass NEONDT8ReqAsmPseudoInst<string opc, string asm, dag iops> {
+  def I8 : NEONDataTypeAsmPseudoInst<opc, ".i8", asm, iops>;
+  def S8 : NEONDataTypeAsmPseudoInst<opc, ".s8", asm, iops>;
+  def U8 : NEONDataTypeAsmPseudoInst<opc, ".u8", asm, iops>;
+  def P8 : NEONDataTypeAsmPseudoInst<opc, ".p8", asm, iops>;
+}
+// NEONDT8ReqAsmPseudoInst plus plain ".8"
+multiclass NEONDT8AsmPseudoInst<string opc, string asm, dag iops> {
+  def _8 : NEONDataTypeAsmPseudoInst<opc, ".8", asm, iops>;
+  defm _ : NEONDT8ReqAsmPseudoInst<opc, asm, iops>;
+}
+multiclass NEONDT16ReqAsmPseudoInst<string opc, string asm, dag iops> {
+  def I16 : NEONDataTypeAsmPseudoInst<opc, ".i16", asm, iops>;
+  def S16 : NEONDataTypeAsmPseudoInst<opc, ".s16", asm, iops>;
+  def U16 : NEONDataTypeAsmPseudoInst<opc, ".u16", asm, iops>;
+  def P16 : NEONDataTypeAsmPseudoInst<opc, ".p16", asm, iops>;
+}
+// NEONDT16ReqAsmPseudoInst plus plain ".16"
+multiclass NEONDT16AsmPseudoInst<string opc, string asm, dag iops> {
+  def _16 : NEONDataTypeAsmPseudoInst<opc, ".16", asm, iops>;
+  defm _ : NEONDT16ReqAsmPseudoInst<opc, asm, iops>;
+}
+multiclass NEONDT32ReqAsmPseudoInst<string opc, string asm, dag iops> {
+  def I32 : NEONDataTypeAsmPseudoInst<opc, ".i32", asm, iops>;
+  def S32 : NEONDataTypeAsmPseudoInst<opc, ".s32", asm, iops>;
+  def U32 : NEONDataTypeAsmPseudoInst<opc, ".u32", asm, iops>;
+  def F32 : NEONDataTypeAsmPseudoInst<opc, ".f32", asm, iops>;
+  def F   : NEONDataTypeAsmPseudoInst<opc, ".f",   asm, iops>;
+}
+// NEONDT32ReqAsmPseudoInst plus plain ".32"
+multiclass NEONDT32AsmPseudoInst<string opc, string asm, dag iops> {
+  def _32 : NEONDataTypeAsmPseudoInst<opc, ".32", asm, iops>;
+  defm _ : NEONDT32ReqAsmPseudoInst<opc, asm, iops>;
+}
+multiclass NEONDT64ReqAsmPseudoInst<string opc, string asm, dag iops> {
+  def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
+  def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
+  def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
+  def F64 : NEONDataTypeAsmPseudoInst<opc, ".f64", asm, iops>;
+  def D   : NEONDataTypeAsmPseudoInst<opc, ".d",   asm, iops>;
+}
+// NEONDT64ReqAsmPseudoInst plus plain ".64"
+multiclass NEONDT64AsmPseudoInst<string opc, string asm, dag iops> {
+  def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
+  defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
+}
+multiclass NEONDT64NoF64ReqAsmPseudoInst<string opc, string asm, dag iops> {
+  def I64 : NEONDataTypeAsmPseudoInst<opc, ".i64", asm, iops>;
+  def S64 : NEONDataTypeAsmPseudoInst<opc, ".s64", asm, iops>;
+  def U64 : NEONDataTypeAsmPseudoInst<opc, ".u64", asm, iops>;
+  def D   : NEONDataTypeAsmPseudoInst<opc, ".d",   asm, iops>;
+}
+// NEONDT64ReqAsmPseudoInst plus plain ".64"
+multiclass NEONDT64NoF64AsmPseudoInst<string opc, string asm, dag iops> {
+  def _64 : NEONDataTypeAsmPseudoInst<opc, ".64", asm, iops>;
+  defm _ : NEONDT64ReqAsmPseudoInst<opc, asm, iops>;
+}
+multiclass NEONDTAnyAsmPseudoInst<string opc, string asm, dag iops> {
+  defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
+  defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
+  defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
+  defm _ : NEONDT64AsmPseudoInst<opc, asm, iops>;
+}
+multiclass NEONDTAnyNoF64AsmPseudoInst<string opc, string asm, dag iops> {
+  defm _ : NEONDT8AsmPseudoInst<opc, asm, iops>;
+  defm _ : NEONDT16AsmPseudoInst<opc, asm, iops>;
+  defm _ : NEONDT32AsmPseudoInst<opc, asm, iops>;
+  defm _ : NEONDT64NoF64AsmPseudoInst<opc, asm, iops>;
 }
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 12efea242b..a395db8868 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -765,13 +765,6 @@ def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
   let Inst{4} = Rn{4};
 }
 
-// FIXME: Proof of concept pseudos. We want to parameterize these for all
-// the suffices we have to support.
-def VLD1LNd8asm : NEONAsmPseudo<"vld1${p}.8 $list, $addr",
-                  (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
-def VLD1LNdf32asm : NEONAsmPseudo<"vld1${p}.f32 $list, $addr",
-                  (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
-
 def VLD1LNq8Pseudo  : VLD1QLNPseudo<v16i8, extloadi8>;
 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
@@ -5599,3 +5592,12 @@ defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
                           (VTRNq16 QPR:$Qd, QPR:$Qm, pred:$p)>;
 defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
                           (VTRNq32 QPR:$Qd, QPR:$Qm, pred:$p)>;
+
+// FIXME: Proof of concept pseudos. We want to parameterize these for all
+// the suffices we have to support.
+defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
+                  (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
+                  (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
+defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
+                  (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 59dec0edfa..33b7eef67c 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4754,8 +4754,22 @@ validateInstruction(MCInst &Inst,
 static unsigned getRealVLDNOpcode(unsigned Opc) {
   switch(Opc) {
   default: assert(0 && "unexpected opcode!");
-  case ARM::VLD1LNd8asm:   return ARM::VLD1LNd8;
-  case ARM::VLD1LNdf32asm: return ARM::VLD1LNd32;
+  case ARM::VLD1LNdAsm_8:   return ARM::VLD1LNd8;
+  case ARM::VLD1LNdAsm_P8:  return ARM::VLD1LNd8;
+  case ARM::VLD1LNdAsm_I8:  return ARM::VLD1LNd8;
+  case ARM::VLD1LNdAsm_S8:  return ARM::VLD1LNd8;
+  case ARM::VLD1LNdAsm_U8:  return ARM::VLD1LNd8;
+  case ARM::VLD1LNdAsm_16:   return ARM::VLD1LNd16;
+  case ARM::VLD1LNdAsm_P16:  return ARM::VLD1LNd16;
+  case ARM::VLD1LNdAsm_I16:  return ARM::VLD1LNd16;
+  case ARM::VLD1LNdAsm_S16:  return ARM::VLD1LNd16;
+  case ARM::VLD1LNdAsm_U16:  return ARM::VLD1LNd16;
+  case ARM::VLD1LNdAsm_32:  return ARM::VLD1LNd32;
+  case ARM::VLD1LNdAsm_F:   return ARM::VLD1LNd32;
+  case ARM::VLD1LNdAsm_F32: return ARM::VLD1LNd32;
+  case ARM::VLD1LNdAsm_I32: return ARM::VLD1LNd32;
+  case ARM::VLD1LNdAsm_S32: return ARM::VLD1LNd32;
+  case ARM::VLD1LNdAsm_U32: return ARM::VLD1LNd32;
   }
 }
 
@@ -4764,8 +4778,22 @@ processInstruction(MCInst &Inst,
                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
   switch (Inst.getOpcode()) {
   // Handle NEON VLD1 complex aliases.
-  case ARM::VLD1LNd8asm:
-  case ARM::VLD1LNdf32asm: {
+  case ARM::VLD1LNdAsm_8:
+  case ARM::VLD1LNdAsm_P8:
+  case ARM::VLD1LNdAsm_I8:
+  case ARM::VLD1LNdAsm_S8:
+  case ARM::VLD1LNdAsm_U8:
+  case ARM::VLD1LNdAsm_16:
+  case ARM::VLD1LNdAsm_P16:
+  case ARM::VLD1LNdAsm_I16:
+  case ARM::VLD1LNdAsm_S16:
+  case ARM::VLD1LNdAsm_U16:
+  case ARM::VLD1LNdAsm_32:
+  case ARM::VLD1LNdAsm_F:
+  case ARM::VLD1LNdAsm_F32:
+  case ARM::VLD1LNdAsm_I32:
+  case ARM::VLD1LNdAsm_S32:
+  case ARM::VLD1LNdAsm_U32: {
     MCInst TmpInst;
     // Shuffle the operands around so the lane index operand is in the
     // right place.
diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s
index 9b831bbe9b..a6c1b6eff9 100644
--- a/test/MC/ARM/neon-vld-encoding.s
+++ b/test/MC/ARM/neon-vld-encoding.s
@@ -182,11 +182,11 @@
 @ CHECK: vld1.8	{d4[], d5[]}, [r1]!     @ encoding: [0x2d,0x4c,0xa1,0xf4]
 @ CHECK: vld1.8	{d4[], d5[]}, [r1], r3  @ encoding: [0x23,0x4c,0xa1,0xf4]
 
-@	vld1.8	{d16[3]}, [r0]
+	vld1.8	{d16[3]}, [r0]
 @	vld1.16	{d16[2]}, [r0, :16]
 @	vld1.32	{d16[1]}, [r0, :32]
 
-@ FIXME: vld1.8	{d16[3]}, [r0]          @ encoding: [0x6f,0x00,0xe0,0xf4]
+@ CHECK: vld1.8	{d16[3]}, [r0]          @ encoding: [0x6f,0x00,0xe0,0xf4]
 @ FIXME: vld1.16 {d16[2]}, [r0, :16]    @ encoding: [0x9f,0x04,0xe0,0xf4]
 @ FIXME: vld1.32 {d16[1]}, [r0, :32]    @ encoding: [0xbf,0x08,0xe0,0xf4]