diff options
| author | Eli Friedman <eli.friedman@gmail.com> | 2010-08-02 00:18:19 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2010-08-02 00:18:19 +0000 |
| commit | e3837014d6793cafdeba99c21dd5682f16131fd5 (patch) | |
| tree | 88b9b33b2cfaf2f717ddf15c6f7d8e03fec067be | |
| parent | 666b40224324f99b011dc7ee08acf254f718e7b1 (diff) | |
| download | llvm-e3837014d6793cafdeba99c21dd5682f16131fd5.tar.gz llvm-e3837014d6793cafdeba99c21dd5682f16131fd5.tar.bz2 llvm-e3837014d6793cafdeba99c21dd5682f16131fd5.tar.xz | |
PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109998 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/vec_constants.ll | 18 |
2 files changed, 14 insertions, 10 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index d47d989b34..33d1441284 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3942,17 +3942,17 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, } // t = vsplti c, result = vsldoi t, t, 1 - if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { + if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) { SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 2 - if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { + if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) { SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 3 - if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { + if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) { SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); } diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll index 32c6f4809c..399f19f8d2 100644 --- a/test/CodeGen/PowerPC/vec_constants.ll +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep CPI -define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { +define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind { %tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] store <4 x i32> %tmp4, <4 x i32>* %P1 @@ -15,26 +15,30 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { ret void } -define <4 x i32> @test_30() { +define <4 x i32> @test_30() nounwind { ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > } -define <4 x i32> @test_29() { +define <4 x i32> @test_29() nounwind { ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > } -define <8 x i16> @test_n30() { +define <8 x i16> @test_n30() nounwind { ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > } -define <16 x i8> @test_n104() { +define <16 x i8> @test_n104() nounwind { ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > } -define <4 x i32> @test_vsldoi() { +define <4 x i32> @test_vsldoi() nounwind { ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > } -define <4 x i32> @test_rol() { +define <8 x i16> @test_vsldoi_65023() nounwind { + ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > +} + +define <4 x i32> @test_rol() nounwind { ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > } |