[PowerPC] Use assembler source in MC tests

A couple of old test cases in test/MC/PowerPC were still using
LLVM IR.  Now that we have a working assembler, we can move
them to assembler tests instead:
  ppc64-initial-cfa.ll
  ppc64-relocs-01.ll
  ppc64-tls-relocs-01.ll




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183829 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 152 insertions, 155 deletions

diff --git a/test/MC/PowerPC/ppc64-initial-cfa.ll b/test/MC/PowerPC/ppc64-initial-cfa.ll
deleted file mode 100644
index 490244d5af..0000000000
--- a/test/MC/PowerPC/ppc64-initial-cfa.ll
+++ /dev/null
@@ -1,87 +0,0 @@
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=static %s -o - | \
-; RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=STATIC
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=pic %s -o - | \
-; RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=PIC
-
-; FIXME: this file should be in .s form, change when asm parser is available.
-
-define void @f() {
-entry:
-  ret void
-}
-
-; STATIC:      Section {
-; STATIC:        Name: .eh_frame
-; STATIC-NEXT:   Type: SHT_PROGBITS
-; STATIC-NEXT:   Flags [ (0x2)
-; STATIC-NEXT:     SHF_ALLOC
-; STATIC-NEXT:   ]
-; STATIC-NEXT:   Address:
-; STATIC-NEXT:   Offset:
-; STATIC-NEXT:   Size: 40
-; STATIC-NEXT:   Link: 0
-; STATIC-NEXT:   Info: 0
-; STATIC-NEXT:   AddressAlignment: 8
-; STATIC-NEXT:   EntrySize: 
-; STATIC-NEXT:   Relocations [
-; STATIC-NEXT:   ]
-; STATIC-NEXT:   SectionData (
-; STATIC-NEXT:     0000: 00000010 00000000 017A5200 01784101
-; STATIC-NEXT:     0010: 1B0C0100 00000010 00000018 00000000
-; STATIC-NEXT:     0020: 00000010 00000000
-; STATIC-NEXT:   )
-; STATIC-NEXT: }
-
-; STATIC:      Section {
-; STATIC:        Name: .rela.eh_frame
-; STATIC-NEXT:   Type: SHT_RELA
-; STATIC-NEXT:   Flags [ (0x0)
-; STATIC-NEXT:   ]
-; STATIC-NEXT:   Address:
-; STATIC-NEXT:   Offset:
-; STATIC-NEXT:   Size: 24
-; STATIC-NEXT:   Link:
-; STATIC-NEXT:   Info:
-; STATIC-NEXT:   AddressAlignment: 8
-; STATIC-NEXT:   EntrySize: 24
-; STATIC-NEXT:   Relocations [
-; STATIC-NEXT:     0x1C R_PPC64_REL32 .text 0x0
-; STATIC-NEXT:   ]
-
-; PIC:      Section {
-; PIC:        Name: .eh_frame
-; PIC-NEXT:   Type: SHT_PROGBITS
-; PIC-NEXT:   Flags [ (0x2)
-; PIC-NEXT:     SHF_ALLOC
-; PIC-NEXT:   ]
-; PIC-NEXT:   Address:
-; PIC-NEXT:   Offset:
-; PIC-NEXT:   Size: 40
-; PIC-NEXT:   Link: 0
-; PIC-NEXT:   Info: 0
-; PIC-NEXT:   AddressAlignment: 8
-; PIC-NEXT:   EntrySize: 0
-; PIC-NEXT:   Relocations [
-; PIC-NEXT:   ]
-; PIC-NEXT:   SectionData (
-; PIC-NEXT:     0000: 00000010 00000000 017A5200 01784101
-; PIC-NEXT:     0010: 1B0C0100 00000010 00000018 00000000
-; PIC-NEXT:     0020: 00000010 00000000
-; PIC-NEXT:   )
-; PIC-NEXT: }
-
-; PIC:      Section {
-; PIC:        Name: .rela.eh_frame
-; PIC-NEXT:   Type: SHT_RELA
-; PIC-NEXT:   Flags [ (0x0)
-; PIC-NEXT:   ]
-; PIC-NEXT:   Address:
-; PIC-NEXT:   Offset:
-; PIC-NEXT:   Size: 24
-; PIC-NEXT:   Link:
-; PIC-NEXT:   Info:
-; PIC-NEXT:   AddressAlignment: 8
-; PIC-NEXT:   EntrySize: 24
-; PIC-NEXT:   Relocations [
-; PIC-NEXT:     0x1C R_PPC64_REL32 .text 0x0
-; PIC-NEXT:   ]
diff --git a/test/MC/PowerPC/ppc64-initial-cfa.s b/test/MC/PowerPC/ppc64-initial-cfa.s
new file mode 100644
index 0000000000..fb45474c16
--- /dev/null
+++ b/test/MC/PowerPC/ppc64-initial-cfa.s
@@ -0,0 +1,84 @@
+# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=static %s | \
+# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=STATIC
+# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=pic %s | \
+# RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=PIC
+
+        .cfi_startproc
+        nop
+        .cfi_endproc
+
+# STATIC:      Section {
+# STATIC:        Name: .eh_frame
+# STATIC-NEXT:   Type: SHT_PROGBITS
+# STATIC-NEXT:   Flags [ (0x2)
+# STATIC-NEXT:     SHF_ALLOC
+# STATIC-NEXT:   ]
+# STATIC-NEXT:   Address:
+# STATIC-NEXT:   Offset:
+# STATIC-NEXT:   Size: 40
+# STATIC-NEXT:   Link: 0
+# STATIC-NEXT:   Info: 0
+# STATIC-NEXT:   AddressAlignment: 8
+# STATIC-NEXT:   EntrySize: 
+# STATIC-NEXT:   Relocations [
+# STATIC-NEXT:   ]
+# STATIC-NEXT:   SectionData (
+# STATIC-NEXT:     0000: 00000010 00000000 017A5200 01784101
+# STATIC-NEXT:     0010: 1B0C0100 00000010 00000018 00000000
+# STATIC-NEXT:     0020: 00000004 00000000
+# STATIC-NEXT:   )
+# STATIC-NEXT: }
+
+# STATIC:      Section {
+# STATIC:        Name: .rela.eh_frame
+# STATIC-NEXT:   Type: SHT_RELA
+# STATIC-NEXT:   Flags [ (0x0)
+# STATIC-NEXT:   ]
+# STATIC-NEXT:   Address:
+# STATIC-NEXT:   Offset:
+# STATIC-NEXT:   Size: 24
+# STATIC-NEXT:   Link:
+# STATIC-NEXT:   Info:
+# STATIC-NEXT:   AddressAlignment: 8
+# STATIC-NEXT:   EntrySize: 24
+# STATIC-NEXT:   Relocations [
+# STATIC-NEXT:     0x1C R_PPC64_REL32 .text 0x0
+# STATIC-NEXT:   ]
+
+# PIC:      Section {
+# PIC:        Name: .eh_frame
+# PIC-NEXT:   Type: SHT_PROGBITS
+# PIC-NEXT:   Flags [ (0x2)
+# PIC-NEXT:     SHF_ALLOC
+# PIC-NEXT:   ]
+# PIC-NEXT:   Address:
+# PIC-NEXT:   Offset:
+# PIC-NEXT:   Size: 40
+# PIC-NEXT:   Link: 0
+# PIC-NEXT:   Info: 0
+# PIC-NEXT:   AddressAlignment: 8
+# PIC-NEXT:   EntrySize: 0
+# PIC-NEXT:   Relocations [
+# PIC-NEXT:   ]
+# PIC-NEXT:   SectionData (
+# PIC-NEXT:     0000: 00000010 00000000 017A5200 01784101
+# PIC-NEXT:     0010: 1B0C0100 00000010 00000018 00000000
+# PIC-NEXT:     0020: 00000004 00000000
+# PIC-NEXT:   )
+# PIC-NEXT: }
+
+# PIC:      Section {
+# PIC:        Name: .rela.eh_frame
+# PIC-NEXT:   Type: SHT_RELA
+# PIC-NEXT:   Flags [ (0x0)
+# PIC-NEXT:   ]
+# PIC-NEXT:   Address:
+# PIC-NEXT:   Offset:
+# PIC-NEXT:   Size: 24
+# PIC-NEXT:   Link:
+# PIC-NEXT:   Info:
+# PIC-NEXT:   AddressAlignment: 8
+# PIC-NEXT:   EntrySize: 24
+# PIC-NEXT:   Relocations [
+# PIC-NEXT:     0x1C R_PPC64_REL32 .text 0x0
+# PIC-NEXT:   ]
diff --git a/test/MC/PowerPC/ppc64-relocs-01.ll b/test/MC/PowerPC/ppc64-relocs-01.ll
deleted file mode 100644
index f4aa347e6c..0000000000
--- a/test/MC/PowerPC/ppc64-relocs-01.ll
+++ /dev/null
@@ -1,49 +0,0 @@
-;; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -O3 -code-model=small  \
-;; RUN:  -filetype=obj %s -o - | \
-;; RUN: llvm-readobj -r | FileCheck %s
-
-;; FIXME: this file need to be in .s form, change when asm parse is done.
-
-@number64 = global i64 10, align 8
-
-define i64 @access_int64(i64 %a) nounwind readonly {
-entry:
-  %0 = load i64* @number64, align 8
-  %cmp = icmp eq i64 %0, %a
-  %conv1 = zext i1 %cmp to i64
-  ret i64 %conv1
-}
-
-declare double @sin(double) nounwind
-
-define double @test_branch24 (double %x) nounwind readonly {
-entry:
-  %add = call double @sin(double %x) nounwind
-  ret double %add
-}
-
-;; CHECK:      Relocations [
-
-;; The relocations in .rela.text are the 'number64' load using a
-;; R_PPC64_TOC16_DS against the .toc and the 'sin' external function
-;; address using a R_PPC64_REL24
-;; CHECK:        Section ({{[0-9]+}}) .rela.text {
-;; CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc
-;; CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_REL24    sin
-;; CHECK-NEXT:   }
-
-;; The .opd entry for the 'access_int64' function creates 2 relocations:
-;; 1. A R_PPC64_ADDR64 against the .text segment plus addend (the function
-;    address itself);
-;; 2. And a R_PPC64_TOC against no symbol (the linker will replace for the
-;;    module's TOC base).
-;; CHECK:        Section ({{[0-9]+}}) .rela.opd {
-;; CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_ADDR64 .text 0x0
-;; CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC - 0x0
-
-;; Finally the TOC creates the relocation for the 'number64'.
-;; CHECK:        Section ({{[0-9]+}}) .rela.toc {
-;; CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_ADDR64 number64 0x0
-;; CHECK-NEXT:   }
-
-;; CHECK-NEXT: ]
diff --git a/test/MC/PowerPC/ppc64-relocs-01.s b/test/MC/PowerPC/ppc64-relocs-01.s
new file mode 100644
index 0000000000..f2e899b834
--- /dev/null
+++ b/test/MC/PowerPC/ppc64-relocs-01.s
@@ -0,0 +1,46 @@
+# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
+# RUN: llvm-readobj -r | FileCheck %s
+
+        .section .opd,"aw",@progbits
+access_int64:
+        .quad .L.access_int64
+        .quad .TOC.@tocbase
+        .quad 0
+        .text
+.L.access_int64:
+        ld 4, .LC1@toc(2)
+        bl sin
+
+        .section .toc,"aw",@progbits
+.LC1:
+        .tc number64[TC],number64
+        .data
+        .globl number64
+number64:
+        .quad	10
+
+# CHECK:      Relocations [
+
+# The relocations in .rela.text are the 'number64' load using a
+# R_PPC64_TOC16_DS against the .toc and the 'sin' external function
+# address using a R_PPC64_REL24
+# CHECK:        Section ({{[0-9]+}}) .rela.text {
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_REL24    sin
+# CHECK-NEXT:   }
+
+# The .opd entry for the 'access_int64' function creates 2 relocations:
+# 1. A R_PPC64_ADDR64 against the .text segment plus addend (the function
+#    address itself);
+# 2. And a R_PPC64_TOC against no symbol (the linker will replace for the
+#    module's TOC base).
+# CHECK:        Section ({{[0-9]+}}) .rela.opd {
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_ADDR64 .text 0x0
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC - 0x0
+
+# Finally the TOC creates the relocation for the 'number64'.
+# CHECK:        Section ({{[0-9]+}}) .rela.toc {
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_ADDR64 number64 0x0
+# CHECK-NEXT:   }
+
+# CHECK-NEXT: ]
diff --git a/test/MC/PowerPC/ppc64-tls-relocs-01.ll b/test/MC/PowerPC/ppc64-tls-relocs-01.ll
deleted file mode 100644
index ae32fa7b89..0000000000
--- a/test/MC/PowerPC/ppc64-tls-relocs-01.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-;; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj %s -o - | \
-;; RUN: llvm-readobj -r | FileCheck %s
-
-;; FIXME: this file should be in .s form, change when asm parser is available.
-
-@t = thread_local global i32 0, align 4
-
-define i32* @f() nounwind {
-entry:
-  ret i32* @t
-}
-
-;; Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
-;; against the thread-local symbol 't'.
-;; CHECK:      Relocations [
-;; CHECK:        Section ({{[0-9]+}}) .rela.text {
-;; CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA t
-;; CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO t
-;; CHECK-NEXT:   }
diff --git a/test/MC/PowerPC/ppc64-tls-relocs-01.s b/test/MC/PowerPC/ppc64-tls-relocs-01.s
new file mode 100644
index 0000000000..66a00fecf3
--- /dev/null
+++ b/test/MC/PowerPC/ppc64-tls-relocs-01.s
@@ -0,0 +1,22 @@
+# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
+# RUN: llvm-readobj -r | FileCheck %s
+
+        .text
+        addis 3, 13, t@tprel@ha
+        addi 3, 3, t@tprel@l
+
+        .type t,@object
+        .section .tbss,"awT",@nobits
+        .globl t
+        .align 2
+t:
+        .long 0
+        .size t, 4
+
+# Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
+# against the thread-local symbol 't'.
+# CHECK:      Relocations [
+# CHECK:        Section ({{[0-9]+}}) .rela.text {
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA t
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO t
+# CHECK-NEXT:   }