diff options
| author | Tim Northover <tnorthover@apple.com> | 2013-05-31 13:47:25 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-05-31 13:47:25 +0000 |
| commit | e93c701cac2ac62bcd390b978604da76be9967d0 (patch) | |
| tree | da4b95d57adc4fa985e00e8f78ec3a581a420234 | |
| parent | b6606e46abad12a112a57048caec2142522bc67d (diff) | |
| download | llvm-e93c701cac2ac62bcd390b978604da76be9967d0.tar.gz llvm-e93c701cac2ac62bcd390b978604da76be9967d0.tar.bz2 llvm-e93c701cac2ac62bcd390b978604da76be9967d0.tar.xz | |
ARM: fix VEXT encoding corner case
The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).
Patch by Amaury de la Vieuville
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 11 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt | 5 |
2 files changed, 11 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 140056a81b..cf8322b300 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -5509,8 +5509,9 @@ class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy> IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "", [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn), (Ty DPR:$Vm), imm:$index)))]> { - bits<4> index; - let Inst{11-8} = index{3-0}; + bits<3> index; + let Inst{11} = 0b0; + let Inst{10-8} = index{2-0}; } class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy> @@ -5525,14 +5526,14 @@ class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy> } def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> { - let Inst{11-8} = index{3-0}; + let Inst{10-8} = index{2-0}; } def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> { - let Inst{11-9} = index{2-0}; + let Inst{10-9} = index{1-0}; let Inst{8} = 0b0; } def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> { - let Inst{11-10} = index{1-0}; + let Inst{10} = index{0}; let Inst{9-8} = 0b00; } def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn), diff --git a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt new file mode 100644 index 0000000000..b76485e4a5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding" + +# invalid imm4 value (0b1xxx) +# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; +0x8f 0xf9 0xf7 0xf2 |