clang-format a bit of code to make the next patch easier to read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203203 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 112 insertions, 128 deletions

diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h
index c2a0f65666..b8fc4d2ddb 100644
--- a/include/llvm/CodeGen/MachineOperand.h
+++ b/include/llvm/CodeGen/MachineOperand.h
@@ -43,22 +43,22 @@ class MCSymbol;
 class MachineOperand {
 public:
   enum MachineOperandType {
-    MO_Register,               ///< Register operand.
-    MO_Immediate,              ///< Immediate operand
-    MO_CImmediate,             ///< Immediate >64bit operand
-    MO_FPImmediate,            ///< Floating-point immediate operand
-    MO_MachineBasicBlock,      ///< MachineBasicBlock reference
-    MO_FrameIndex,             ///< Abstract Stack Frame Index
-    MO_ConstantPoolIndex,      ///< Address of indexed Constant in Constant Pool
-    MO_TargetIndex,            ///< Target-dependent index+offset operand.
-    MO_JumpTableIndex,         ///< Address of indexed Jump Table for switch
-    MO_ExternalSymbol,         ///< Name of external global symbol
-    MO_GlobalAddress,          ///< Address of a global value
-    MO_BlockAddress,           ///< Address of a basic block
-    MO_RegisterMask,           ///< Mask of preserved registers.
-    MO_RegisterLiveOut,        ///< Mask of live-out registers.
-    MO_Metadata,               ///< Metadata reference (for debug info)
-    MO_MCSymbol                ///< MCSymbol reference (for debug/eh info)
+    MO_Register,          ///< Register operand.
+    MO_Immediate,         ///< Immediate operand
+    MO_CImmediate,        ///< Immediate >64bit operand
+    MO_FPImmediate,       ///< Floating-point immediate operand
+    MO_MachineBasicBlock, ///< MachineBasicBlock reference
+    MO_FrameIndex,        ///< Abstract Stack Frame Index
+    MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
+    MO_TargetIndex,       ///< Target-dependent index+offset operand.
+    MO_JumpTableIndex,    ///< Address of indexed Jump Table for switch
+    MO_ExternalSymbol,    ///< Name of external global symbol
+    MO_GlobalAddress,     ///< Address of a global value
+    MO_BlockAddress,      ///< Address of a basic block
+    MO_RegisterMask,      ///< Mask of preserved registers.
+    MO_RegisterLiveOut,   ///< Mask of live-out registers.
+    MO_Metadata,          ///< Metadata reference (for debug info)
+    MO_MCSymbol           ///< MCSymbol reference (for debug/eh info)
   };
 
 private:
@@ -150,13 +150,13 @@ private:
 
   /// Contents union - This contains the payload for the various operand types.
   union {
-    MachineBasicBlock *MBB;   // For MO_MachineBasicBlock.
-    const ConstantFP *CFP;    // For MO_FPImmediate.
-    const ConstantInt *CI;    // For MO_CImmediate. Integers > 64bit.
-    int64_t ImmVal;           // For MO_Immediate.
-    const uint32_t *RegMask;  // For MO_RegisterMask and MO_RegisterLiveOut.
-    const MDNode *MD;         // For MO_Metadata.
-    MCSymbol *Sym;            // For MO_MCSymbol
+    MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
+    const ConstantFP *CFP;   // For MO_FPImmediate.
+    const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
+    int64_t ImmVal;          // For MO_Immediate.
+    const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
+    const MDNode *MD;        // For MO_Metadata.
+    MCSymbol *Sym;           // For MO_MCSymbol
 
     struct {                  // For MO_Register.
       // Register number is in SmallContents.RegNo.
diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h
index bd74cb9c0f..d6225a4bc0 100644
--- a/include/llvm/Target/TargetOpcodes.h
+++ b/include/llvm/Target/TargetOpcodes.h
@@ -22,90 +22,90 @@ namespace llvm {
 /// must be the same as in CodeGenTarget.cpp.
 ///
 namespace TargetOpcode {
-  enum {
-    PHI = 0,
-    INLINEASM = 1,
-    PROLOG_LABEL = 2,
-    EH_LABEL = 3,
-    GC_LABEL = 4,
-
-    /// KILL - This instruction is a noop that is used only to adjust the
-    /// liveness of registers. This can be useful when dealing with
-    /// sub-registers.
-    KILL = 5,
-
-    /// EXTRACT_SUBREG - This instruction takes two operands: a register
-    /// that has subregisters, and a subregister index. It returns the
-    /// extracted subregister value. This is commonly used to implement
-    /// truncation operations on target architectures which support it.
-    EXTRACT_SUBREG = 6,
-
-    /// INSERT_SUBREG - This instruction takes three operands: a register that
-    /// has subregisters, a register providing an insert value, and a
-    /// subregister index. It returns the value of the first register with the
-    /// value of the second register inserted. The first register is often
-    /// defined by an IMPLICIT_DEF, because it is commonly used to implement
-    /// anyext operations on target architectures which support it.
-    INSERT_SUBREG = 7,
-
-    /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
-    IMPLICIT_DEF = 8,
-
-    /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
-    /// the first operand is an immediate integer constant. This constant is
-    /// often zero, because it is commonly used to assert that the instruction
-    /// defining the register implicitly clears the high bits.
-    SUBREG_TO_REG = 9,
-
-    /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
-    /// register-to-register copy into a specific register class. This is only
-    /// used between instruction selection and MachineInstr creation, before
-    /// virtual registers have been created for all the instructions, and it's
-    /// only needed in cases where the register classes implied by the
-    /// instructions are insufficient. It is emitted as a COPY MachineInstr.
-    COPY_TO_REGCLASS = 10,
-
-    /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
-    DBG_VALUE = 11,
-
-    /// REG_SEQUENCE - This variadic instruction is used to form a register that
-    /// represents a consecutive sequence of sub-registers. It's used as a
-    /// register coalescing / allocation aid and must be eliminated before code
-    /// emission.
-    // In SDNode form, the first operand encodes the register class created by
-    // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
-    // pair.  Once it has been lowered to a MachineInstr, the regclass operand
-    // is no longer present.
-    /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
-    /// After register coalescing references of v1024 should be replace with
-    /// v1027:3, v1025 with v1027:4, etc.
-    REG_SEQUENCE = 12,
-
-    /// COPY - Target-independent register copy. This instruction can also be
-    /// used to copy between subregisters of virtual registers.
-    COPY = 13,
-
-    /// BUNDLE - This instruction represents an instruction bundle. Instructions
-    /// which immediately follow a BUNDLE instruction which are marked with
-    /// 'InsideBundle' flag are inside the bundle.
-    BUNDLE = 14,
-
-    /// Lifetime markers.
-    LIFETIME_START = 15,
-    LIFETIME_END = 16,
-
-    /// A Stackmap instruction captures the location of live variables at its
-    /// position in the instruction stream. It is followed by a shadow of bytes
-    /// that must lie within the function and not contain another stackmap.
-    STACKMAP = 17,
-
-    /// Patchable call instruction - this instruction represents a call to a
-    /// constant address, followed by a series of NOPs. It is intended to
-    /// support optimizations for dynamic languages (such as javascript) that
-    /// rewrite calls to runtimes with more efficient code sequences.
-    /// This also implies a stack map.
-    PATCHPOINT = 18
-  };
+enum {
+  PHI = 0,
+  INLINEASM = 1,
+  PROLOG_LABEL = 2,
+  EH_LABEL = 3,
+  GC_LABEL = 4,
+
+  /// KILL - This instruction is a noop that is used only to adjust the
+  /// liveness of registers. This can be useful when dealing with
+  /// sub-registers.
+  KILL = 5,
+
+  /// EXTRACT_SUBREG - This instruction takes two operands: a register
+  /// that has subregisters, and a subregister index. It returns the
+  /// extracted subregister value. This is commonly used to implement
+  /// truncation operations on target architectures which support it.
+  EXTRACT_SUBREG = 6,
+
+  /// INSERT_SUBREG - This instruction takes three operands: a register that
+  /// has subregisters, a register providing an insert value, and a
+  /// subregister index. It returns the value of the first register with the
+  /// value of the second register inserted. The first register is often
+  /// defined by an IMPLICIT_DEF, because it is commonly used to implement
+  /// anyext operations on target architectures which support it.
+  INSERT_SUBREG = 7,
+
+  /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
+  IMPLICIT_DEF = 8,
+
+  /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
+  /// the first operand is an immediate integer constant. This constant is
+  /// often zero, because it is commonly used to assert that the instruction
+  /// defining the register implicitly clears the high bits.
+  SUBREG_TO_REG = 9,
+
+  /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
+  /// register-to-register copy into a specific register class. This is only
+  /// used between instruction selection and MachineInstr creation, before
+  /// virtual registers have been created for all the instructions, and it's
+  /// only needed in cases where the register classes implied by the
+  /// instructions are insufficient. It is emitted as a COPY MachineInstr.
+  COPY_TO_REGCLASS = 10,
+
+  /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
+  DBG_VALUE = 11,
+
+  /// REG_SEQUENCE - This variadic instruction is used to form a register that
+  /// represents a consecutive sequence of sub-registers. It's used as a
+  /// register coalescing / allocation aid and must be eliminated before code
+  /// emission.
+  // In SDNode form, the first operand encodes the register class created by
+  // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
+  // pair.  Once it has been lowered to a MachineInstr, the regclass operand
+  // is no longer present.
+  /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
+  /// After register coalescing references of v1024 should be replace with
+  /// v1027:3, v1025 with v1027:4, etc.
+  REG_SEQUENCE = 12,
+
+  /// COPY - Target-independent register copy. This instruction can also be
+  /// used to copy between subregisters of virtual registers.
+  COPY = 13,
+
+  /// BUNDLE - This instruction represents an instruction bundle. Instructions
+  /// which immediately follow a BUNDLE instruction which are marked with
+  /// 'InsideBundle' flag are inside the bundle.
+  BUNDLE = 14,
+
+  /// Lifetime markers.
+  LIFETIME_START = 15,
+  LIFETIME_END = 16,
+
+  /// A Stackmap instruction captures the location of live variables at its
+  /// position in the instruction stream. It is followed by a shadow of bytes
+  /// that must lie within the function and not contain another stackmap.
+  STACKMAP = 17,
+
+  /// Patchable call instruction - this instruction represents a call to a
+  /// constant address, followed by a series of NOPs. It is intended to
+  /// support optimizations for dynamic languages (such as javascript) that
+  /// rewrite calls to runtimes with more efficient code sequences.
+  /// This also implies a stack map.
+  PATCHPOINT = 18
+};
 } // end namespace TargetOpcode
 } // end namespace llvm
 
diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index 92b3f05a28..6f6acaa85f 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -294,27 +294,11 @@ GetInstByName(const char *Name,
 void CodeGenTarget::ComputeInstrsByEnum() const {
   // The ordering here must match the ordering in TargetOpcodes.h.
   static const char *const FixedInstrs[] = {
-    "PHI",
-    "INLINEASM",
-    "PROLOG_LABEL",
-    "EH_LABEL",
-    "GC_LABEL",
-    "KILL",
-    "EXTRACT_SUBREG",
-    "INSERT_SUBREG",
-    "IMPLICIT_DEF",
-    "SUBREG_TO_REG",
-    "COPY_TO_REGCLASS",
-    "DBG_VALUE",
-    "REG_SEQUENCE",
-    "COPY",
-    "BUNDLE",
-    "LIFETIME_START",
-    "LIFETIME_END",
-    "STACKMAP",
-    "PATCHPOINT",
-    0
-  };
+      "PHI",          "INLINEASM",     "PROLOG_LABEL",     "EH_LABEL",
+      "GC_LABEL",     "KILL",          "EXTRACT_SUBREG",   "INSERT_SUBREG",
+      "IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
+      "REG_SEQUENCE", "COPY",          "BUNDLE",           "LIFETIME_START",
+      "LIFETIME_END", "STACKMAP",      "PATCHPOINT",       0};
   const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
   for (const char *const *p = FixedInstrs; *p; ++p) {
     const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);