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author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-05-21 09:58:54 +0000 |
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committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-05-21 09:58:54 +0000 |
commit | f106d8bad6ba3759e512e1a1e6cc09ce832bd74e (patch) | |
tree | 24e57a132dba22972e3255754d6863022d7c0ab5 | |
parent | af2a1bebfcef3e3767ef3875957c986e087dd0e8 (diff) | |
download | llvm-f106d8bad6ba3759e512e1a1e6cc09ce832bd74e.tar.gz llvm-f106d8bad6ba3759e512e1a1e6cc09ce832bd74e.tar.bz2 llvm-f106d8bad6ba3759e512e1a1e6cc09ce832bd74e.tar.xz |
X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type.
Otherwise we'll get a mix of signed and unsigned compares.
Fixes PR15977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182364 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 34 | ||||
-rw-r--r-- | test/CodeGen/X86/vec_compare.ll | 10 |
2 files changed, 27 insertions, 17 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e05cde7a86..1f35056f21 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -9347,29 +9347,24 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, if (Swap) std::swap(Op0, Op1); - // Since SSE has no unsigned integer comparisons, we need to flip the sign - // bits of the inputs before performing those operations. - if (FlipSigns) { - EVT EltVT = VT.getVectorElementType(); - SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), - EltVT); - std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); - SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], - SignBits.size()); - Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); - Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); - } - // Check that the operation in question is available (most are plain SSE2, // but PCMPGTQ and PCMPEQQ have different requirements). if (VT == MVT::v2i64) { if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) { assert(Subtarget->hasSSE2() && "Don't know how to lower!"); - // First cast everything to the right type, + // First cast everything to the right type. Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0); Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); + // Since SSE has no unsigned integer comparisons, we need to flip the sign + // bits of the inputs before performing those operations. + if (FlipSigns) { + SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32); + Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB); + Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB); + } + // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2)) SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1); SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1); @@ -9395,7 +9390,7 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, // pcmpeqd + pshufd + pand. assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!"); - // First cast everything to the right type, + // First cast everything to the right type. Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0); Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1); @@ -9414,6 +9409,15 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, } } + // Since SSE has no unsigned integer comparisons, we need to flip the sign + // bits of the inputs before performing those operations. + if (FlipSigns) { + EVT EltVT = VT.getVectorElementType(); + SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT); + Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB); + Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB); + } + SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); // If the logical-not of the result is required, perform that now. diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll index 85d8b2cea3..9532499786 100644 --- a/test/CodeGen/X86/vec_compare.ll +++ b/test/CodeGen/X86/vec_compare.ll @@ -131,9 +131,15 @@ define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind { } define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: [[CONSTSEG:[A-Z0-9_]*]]: +; CHECK: .long 2147483648 +; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 2147483648 ; CHECK: test11: -; CHECK: pxor -; CHECK: pxor +; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]] +; CHECK: pxor [[CONSTREG]] +; CHECK: pxor [[CONSTREG]] ; CHECK: pcmpgtd %xmm1 ; CHECK: pshufd $-96 ; CHECK: pcmpeqd |