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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-08-12 10:05:58 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-08-12 10:05:58 +0000 |
| commit | f37c8feb468a0e1876c08bdeb449bdb5999c0534 (patch) | |
| tree | 681b3c2a059c42b44376e4004bc4f1cb222f25d3 | |
| parent | 8d8bdff6d7eccb05bf16e18141263ee72ea8296b (diff) | |
| download | llvm-f37c8feb468a0e1876c08bdeb449bdb5999c0534.tar.gz llvm-f37c8feb468a0e1876c08bdeb449bdb5999c0534.tar.bz2 llvm-f37c8feb468a0e1876c08bdeb449bdb5999c0534.tar.xz | |
[SystemZ] Add a definition of the IPM instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188161 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrFP.td | 6 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrFormats.td | 2 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 4 | ||||
| -rw-r--r-- | test/MC/Disassembler/SystemZ/insns.txt | 9 | ||||
| -rw-r--r-- | test/MC/SystemZ/insn-good.s | 8 |
5 files changed, 25 insertions, 4 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td index b903b51975..9f5279e63a 100644 --- a/lib/Target/SystemZ/SystemZInstrFP.td +++ b/lib/Target/SystemZ/SystemZInstrFP.td @@ -27,9 +27,9 @@ defm CondStoreF64 : CondStores<FP64, nonvolatile_store, // Load zero. let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { - def LZER : InherentRRE<"lze", 0xB374, FP32, (fpimm0)>; - def LZDR : InherentRRE<"lzd", 0xB375, FP64, (fpimm0)>; - def LZXR : InherentRRE<"lzx", 0xB376, FP128, (fpimm0)>; + def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>; + def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>; + def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>; } // Moves between two floating-point registers. diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index 954df11269..2af8e83aed 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -552,7 +552,7 @@ class InstSS<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, dag src> : InstRRE<opcode, (outs cls:$R1), (ins), - mnemonic#"r\t$R1", + mnemonic#"\t$R1", [(set cls:$R1, src)]> { let R2 = 0; } diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index b318d674f3..5371e8ad4d 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1119,6 +1119,10 @@ let Defs = [CC] in { // Miscellaneous Instructions. //===----------------------------------------------------------------------===// +// Extract CC into bits 29 and 28 of a register. +let Uses = [CC] in + def IPM : InherentRRE<"ipm", 0xB222, GR32, (null_frag)>; + // Read a 32-bit access register into a GR32. As with all GR32 operations, // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful // when a 64-bit address is stored in a pair of access registers. diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index 51860cc5d1..97e41fee12 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -2260,6 +2260,15 @@ # CHECK: iill %r15, 0 0xa5 0xf3 0x00 0x00 +# CHECK: ipm %r0 +0xb2 0x22 0x00 0x00 + +# CHECK: ipm %r1 +0xb2 0x22 0x00 0x10 + +# CHECK: ipm %r15 +0xb2 0x22 0x00 0xf0 + # CHECK: la %r0, 0 0x41 0x00 0x00 0x00 diff --git a/test/MC/SystemZ/insn-good.s b/test/MC/SystemZ/insn-good.s index c997271bb6..c4e09e4778 100644 --- a/test/MC/SystemZ/insn-good.s +++ b/test/MC/SystemZ/insn-good.s @@ -3593,6 +3593,14 @@ iill %r0, 0xffff iill %r15, 0 +#CHECK: ipm %r0 # encoding: [0xb2,0x22,0x00,0x00] +#CHECK: ipm %r1 # encoding: [0xb2,0x22,0x00,0x10] +#CHECK: ipm %r15 # encoding: [0xb2,0x22,0x00,0xf0] + + ipm %r0 + ipm %r1 + ipm %r15 + #CHECK: l %r0, 0 # encoding: [0x58,0x00,0x00,0x00] #CHECK: l %r0, 4095 # encoding: [0x58,0x00,0x0f,0xff] #CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00] |