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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-01-15 13:01:18 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-01-15 13:01:18 +0000 |
| commit | f5c2d3896b8af35409b7c1b11c3811c459b0ccd1 (patch) | |
| tree | fbd70a4cac93a454fb956a309767cecc8e019d3c | |
| parent | 9ac0e23865889b4668e2661a0d01091ef1559d6d (diff) | |
| download | llvm-f5c2d3896b8af35409b7c1b11c3811c459b0ccd1.tar.gz llvm-f5c2d3896b8af35409b7c1b11c3811c459b0ccd1.tar.bz2 llvm-f5c2d3896b8af35409b7c1b11c3811c459b0ccd1.tar.xz | |
Added support for LWU microMIPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199315 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MicroMipsInstrInfo.td | 12 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/micromips.txt | 3 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/micromips_le.txt | 3 | ||||
| -rw-r--r-- | test/MC/Mips/micromips-loadstore-instructions.s | 3 |
4 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 84cba5fb20..ffcf48bf98 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -60,6 +60,16 @@ class SCBaseMM<string opstr, RegisterOperand RO> : let Constraints = "$rt = $dst"; } +class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, + InstrItinClass Itin = NoItinerary> : + InstSE<(outs RO:$rt), (ins mem_mm_12:$addr), + !strconcat(opstr, "\t$rt, $addr"), + [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> { + let DecoderMethod = "DecodeMemMMImm12"; + let canFoldAsLoad = 1; + let mayLoad = 1; +} + let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Arithmetic Instructions (ALU Immediate) def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>, @@ -136,6 +146,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>; } + def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, IILoad>, LL_FM_MM<0xe>; + /// Load and Store Instructions - unaligned def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>, LWL_FM_MM<0x0>; diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt index b2d0cc02fc..91d06162a1 100644 --- a/test/MC/Disassembler/Mips/micromips.txt +++ b/test/MC/Disassembler/Mips/micromips.txt @@ -145,6 +145,9 @@ # CHECK: sw $5, 4($6) 0xf8 0xa6 0x00 0x04 +# CHECK: lwu $2, 8($4) +0x60 0x44 0xe0 0x08 + # CHECK: lwl $4, 16($5) 0x60 0x85 0x00 0x10 diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt index 5b2fe30dd0..f32eb38c14 100644 --- a/test/MC/Disassembler/Mips/micromips_le.txt +++ b/test/MC/Disassembler/Mips/micromips_le.txt @@ -145,6 +145,9 @@ # CHECK: sw $5, 4($6) 0xa6 0xf8 0x04 0x00 +# CHECK: lwu $2, 8($4) +0x44 0x60 0x08 0xe0 + # CHECK: lwl $4, 16($5) 0x85 0x60 0x10 0x00 diff --git a/test/MC/Mips/micromips-loadstore-instructions.s b/test/MC/Mips/micromips-loadstore-instructions.s index 4885e4e34d..8a1b93babd 100644 --- a/test/MC/Mips/micromips-loadstore-instructions.s +++ b/test/MC/Mips/micromips-loadstore-instructions.s @@ -19,6 +19,7 @@ # CHECK-EL: sw $5, 4($6) # encoding: [0xa6,0xf8,0x04,0x00] # CHECK-EL: ll $2, 8($4) # encoding: [0x44,0x60,0x08,0x30] # CHECK-EL: sc $2, 8($4) # encoding: [0x44,0x60,0x08,0xb0] +# CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -32,6 +33,7 @@ # CHECK-EB: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] # CHECK-EB: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] # CHECK-EB: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] +# CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08] lb $5, 8($4) lbu $6, 8($4) lh $2, 8($4) @@ -42,3 +44,4 @@ sw $5, 4($6) ll $2, 8($4) sc $2, 8($4) + lwu $2, 8($4) |