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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-17 20:23:23 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-17 20:23:23 +0000 |
| commit | f9b9abbd08ea36f2226c6e21cd0113ea015944e0 (patch) | |
| tree | 84221165222fc2485ec26be2f4f61397db5cd8fc | |
| parent | 32ab4aff69f4bb51cdd9196800da485f094a5ccb (diff) | |
| download | llvm-f9b9abbd08ea36f2226c6e21cd0113ea015944e0.tar.gz llvm-f9b9abbd08ea36f2226c6e21cd0113ea015944e0.tar.bz2 llvm-f9b9abbd08ea36f2226c6e21cd0113ea015944e0.tar.xz | |
Add CHECKs and document PR11158.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142240 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/CodeGen/ARM/vrev.ll | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index 5c3c0fca10..e154334970 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -148,8 +148,13 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind { ret void } -; vrev <4 x i16> should use VREV32 and not VREV64 +; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored +; to <2 x i16> when stored to memory. Currently ARM scalarizes these stores. +; See PR 11158 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { +; CHECK: test_vrev64: +; CHECK: vst1.16 +; CHECK: vst1.16 entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* %tmp2 = load <8 x i16>* %0, align 4 |