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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-09-29 00:40:51 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-09-29 00:40:51 +0000 |
| commit | 3627a462938c92c00053a24828b35da5195d0d68 (patch) | |
| tree | 71a5f1b55df01fb7c412ecc91f12037b601483bb /configure | |
| parent | caf191289365ba6f551969baf1dad22238820e75 (diff) | |
| download | llvm-3627a462938c92c00053a24828b35da5195d0d68.tar.gz llvm-3627a462938c92c00053a24828b35da5195d0d68.tar.bz2 llvm-3627a462938c92c00053a24828b35da5195d0d68.tar.xz | |
Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.
This also fixes a bug when adding operands after an implicit operand has
been added manually. The NumImplicitOps count wasn't kept up to date.
MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added. It is possible to change an MI opcode and add additional
explicit operands. They will be inserted before any existing implicit
operands.
The only exception is inline asm instructions where operands are never
reordered. This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140744 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'configure')
0 files changed, 0 insertions, 0 deletions