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| author | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:42:26 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:42:26 +0000 |
| commit | 9105f66d6f3cb6330ce77a88a0ef1ec0744aba85 (patch) | |
| tree | d3360e2214cbc002d9587dba967b7ec514aeb997 /configure | |
| parent | 4ca8b0b66defbeff6693ce1fc68436a836939a53 (diff) | |
| download | llvm-9105f66d6f3cb6330ce77a88a0ef1ec0744aba85.tar.gz llvm-9105f66d6f3cb6330ce77a88a0ef1ec0744aba85.tar.bz2 llvm-9105f66d6f3cb6330ce77a88a0ef1ec0744aba85.tar.xz | |
AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.
The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.
Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209576 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'configure')
| -rwxr-xr-x | configure | 14 |
1 files changed, 6 insertions, 8 deletions
@@ -4153,7 +4153,7 @@ else powerpc*-*) llvm_cv_target_arch="PowerPC" ;; arm64*-*) llvm_cv_target_arch="ARM64" ;; arm*-*) llvm_cv_target_arch="ARM" ;; - aarch64*-*) llvm_cv_target_arch="AArch64" ;; + aarch64*-*) llvm_cv_target_arch="ARM64" ;; mips-* | mips64-*) llvm_cv_target_arch="Mips" ;; mipsel-* | mips64el-*) llvm_cv_target_arch="Mips" ;; xcore-*) llvm_cv_target_arch="XCore" ;; @@ -4190,7 +4190,7 @@ case $host in powerpc*-*) host_arch="PowerPC" ;; arm64*-*) host_arch="ARM64" ;; arm*-*) host_arch="ARM" ;; - aarch64*-*) host_arch="AArch64" ;; + aarch64*-*) host_arch="ARM64" ;; mips-* | mips64-*) host_arch="Mips" ;; mipsel-* | mips64el-*) host_arch="Mips" ;; xcore-*) host_arch="XCore" ;; @@ -5103,8 +5103,6 @@ else ;; ARM) TARGET_HAS_JIT=1 ;; - AArch64) TARGET_HAS_JIT=0 - ;; Mips) TARGET_HAS_JIT=1 ;; XCore) TARGET_HAS_JIT=0 @@ -5122,7 +5120,7 @@ else esac fi -TARGETS_WITH_JIT="AArch64 ARM ARM64 Mips PowerPC SystemZ X86" +TARGETS_WITH_JIT="ARM ARM64 Mips PowerPC SystemZ X86" TARGETS_WITH_JIT=$TARGETS_WITH_JIT @@ -5359,7 +5357,7 @@ _ACEOF fi -ALL_TARGETS="X86 Sparc PowerPC AArch64 ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" +ALL_TARGETS="X86 Sparc PowerPC ARM ARM64 Mips XCore MSP430 CppBackend NVPTX Hexagon SystemZ R600" ALL_TARGETS=$ALL_TARGETS @@ -5382,7 +5380,7 @@ case "$enableval" in x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;; powerpc) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;; - aarch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;; + aarch64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;; arm64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;; arm) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;; mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;; @@ -5401,7 +5399,7 @@ case "$enableval" in x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; Sparc) TARGETS_TO_BUILD="Sparc $TARGETS_TO_BUILD" ;; PowerPC) TARGETS_TO_BUILD="PowerPC $TARGETS_TO_BUILD" ;; - AArch64) TARGETS_TO_BUILD="AArch64 $TARGETS_TO_BUILD" ;; + AArch64) TARGETS_TO_BUILD="ARM64 $TARGETS_TO_BUILD" ;; ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;; Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;; XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;; |