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| author | Wesley Peck <peckw@wesleypeck.com> | 2010-02-23 19:15:24 +0000 |
|---|---|---|
| committer | Wesley Peck <peckw@wesleypeck.com> | 2010-02-23 19:15:24 +0000 |
| commit | a70f28ce7dc85d0075a7d86da5d7987b6e306bc6 (patch) | |
| tree | fe6fdbcfb4cb0969874e482a41654e709108ef40 /configure | |
| parent | 2cce3712fafb2e72e144414377cd48f5ab95a5ae (diff) | |
| download | llvm-a70f28ce7dc85d0075a7d86da5d7987b6e306bc6.tar.gz llvm-a70f28ce7dc85d0075a7d86da5d7987b6e306bc6.tar.bz2 llvm-a70f28ce7dc85d0075a7d86da5d7987b6e306bc6.tar.xz | |
Adding the MicroBlaze backend.
The MicroBlaze is a highly configurable 32-bit soft-microprocessor for
use on Xilinx FPGAs. For more information see:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze
The current LLVM MicroBlaze backend generates assembly which can be
compiled using the an appropriate binutils assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96969 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'configure')
| -rwxr-xr-x | configure | 7 |
1 files changed, 6 insertions, 1 deletions
@@ -2330,6 +2330,7 @@ else msp430-*) llvm_cv_target_arch="MSP430" ;; s390x-*) llvm_cv_target_arch="SystemZ" ;; bfin-*) llvm_cv_target_arch="Blackfin" ;; + microblaze-*) llvm_cv_target_arch="MBlaze" ;; *) llvm_cv_target_arch="Unknown" ;; esac fi @@ -4795,6 +4796,8 @@ else ;; Blackfin) TARGET_HAS_JIT=0 ;; + MBlaze) TARGET_HAS_JIT=0 + ;; *) TARGET_HAS_JIT=0 ;; esac @@ -4898,7 +4901,7 @@ if test "$enableval" = host-only ; then enableval=host fi case "$enableval" in - all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend" ;; + all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend MBlaze" ;; *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do case "$a_target" in x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; @@ -4917,6 +4920,7 @@ case "$enableval" in cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;; msil) TARGETS_TO_BUILD="MSIL $TARGETS_TO_BUILD" ;; cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;; + mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;; host) case "$llvm_cv_target_arch" in x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; @@ -4925,6 +4929,7 @@ case "$enableval" in Alpha) TARGETS_TO_BUILD="Alpha $TARGETS_TO_BUILD" ;; ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;; Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;; + MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;; CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;; PIC16) TARGETS_TO_BUILD="PIC16 $TARGETS_TO_BUILD" ;; XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;; |