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| author | Bill Wendling <isanbard@gmail.com> | 2006-10-11 06:30:10 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2006-10-11 06:30:10 +0000 |
| commit | 3cd5ca6c72787fa4e5fd2b8d880545f8863f35d1 (patch) | |
| tree | 08bd9cec27dcc717d7fb3b42f511e291616d02ff /docs/CodeGenerator.html | |
| parent | d615ded96ed2ee8e6537a7132a5364a29f37b46e (diff) | |
| download | llvm-3cd5ca6c72787fa4e5fd2b8d880545f8863f35d1.tar.gz llvm-3cd5ca6c72787fa4e5fd2b8d880545f8863f35d1.tar.bz2 llvm-3cd5ca6c72787fa4e5fd2b8d880545f8863f35d1.tar.xz | |
Put code example inside of "doc_code" divisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30876 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs/CodeGenerator.html')
| -rw-r--r-- | docs/CodeGenerator.html | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index 405c57b345..ebee043315 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1227,7 +1227,16 @@ defining instruction is encountered.</p> </div> <div class="doc_text"> -<p>To Be Written</p> + +<p>We now have the information available to perform the liver intervals analysis +and build the live intervals themselves. We start off by numbering the basic +blocks and machine instructions. We then handle the "live-in" values. These +are in physical registers, so the physical register is assumed to be killed by +the end of the basic block. Live intervals for virtual registers are computed +for some ordering of the machine instructions <tt>[1,N]</tt>. A live interval +is an interval <tt>[i,j)</tt>, where <tt>1 <= i <= j < N</tt>, for which a +variable is live.</p> + </ol> </div> @@ -1239,14 +1248,14 @@ defining instruction is encountered.</p> <div class="doc_text"> -<p>The <i>Register Allocation problem</i> consists in mapping a -program <i>P<sub>v</sub></i>, that can use an unbounded number of -virtual registers, to a program <i>P<sub>p</sub></i> that contains a -finite (possibly small) number of physical registers. Each target -architecture has a different number of physical registers. If the -number of physical registers is not enough to accommodate all the -virtual registers, some of them will have to be mapped into -memory. These virtuals are called <i>spilled virtuals</i>.</p> +<p>The <i>Register Allocation problem</i> consists in mapping a program +<i>P<sub>v</sub></i>, that can use an unbounded number of virtual +registers, to a program <i>P<sub>p</sub></i> that contains a finite +(possibly small) number of physical registers. Each target architecture has +a different number of physical registers. If the number of physical +registers is not enough to accommodate all the virtual registers, some of +them will have to be mapped into memory. These virtuals are called +<i>spilled virtuals</i>.</p> </div> |