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authorEli Bendersky <eliben@google.com>2012-10-31 16:41:07 +0000
committerEli Bendersky <eliben@google.com>2012-10-31 16:41:07 +0000
commit97d6abee58da99c41b26b99d724d026d4c73791a (patch)
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Fix typo in CodeGenerator doc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167137 91177308-0d34-0410-b5e6-96231b3b80d8
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diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst
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@@ -256,10 +256,10 @@ The ``TargetRegisterInfo`` class
The ``TargetRegisterInfo`` class is used to describe the register file of the
target and any interactions between the registers.
-Registers in the code generator are represented in the code generator by
-unsigned integers. Physical registers (those that actually exist in the target
-description) are unique small numbers, and virtual registers are generally
-large. Note that register ``#0`` is reserved as a flag value.
+Registers are represented in the code generator by unsigned integers. Physical
+registers (those that actually exist in the target description) are unique
+small numbers, and virtual registers are generally large. Note that
+register ``#0`` is reserved as a flag value.
Each register in the processor description has an associated
``TargetRegisterDesc`` entry, which provides a textual name for the register