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| author | Sean Silva <silvas@purdue.edu> | 2014-04-07 22:46:40 +0000 |
|---|---|---|
| committer | Sean Silva <silvas@purdue.edu> | 2014-04-07 22:46:40 +0000 |
| commit | b9a65fd0028acd588f8382a50f7271e332fc363d (patch) | |
| tree | d0a4849fa44fcb7959433686d42d16a5c98d5df1 /docs/CodeGenerator.rst | |
| parent | ba9e79f7ef5b73612459b61bf34046a64aff37db (diff) | |
| download | llvm-b9a65fd0028acd588f8382a50f7271e332fc363d.tar.gz llvm-b9a65fd0028acd588f8382a50f7271e332fc363d.tar.bz2 llvm-b9a65fd0028acd588f8382a50f7271e332fc363d.tar.xz | |
[docs] Fix some links
The TableGen docs have changed structure
Patch by Tay Ray Chuan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205744 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs/CodeGenerator.rst')
| -rw-r--r-- | docs/CodeGenerator.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst index d7d98bc385..58906c2749 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -172,7 +172,7 @@ architecture. These target descriptions often have a large amount of common information (e.g., an ``add`` instruction is almost identical to a ``sub`` instruction). In order to allow the maximum amount of commonality to be factored out, the LLVM code generator uses the -:doc:`TableGen <TableGenFundamentals>` tool to describe big chunks of the +:doc:`TableGen/index` tool to describe big chunks of the target machine, which allows the use of domain-specific and target-specific abstractions to reduce the amount of repetition. @@ -277,7 +277,7 @@ an associated register class. When the register allocator runs, it replaces virtual registers with a physical register in the set. The target-specific implementations of these classes is auto-generated from a -`TableGen <TableGenFundamentals.html>`_ description of the register file. +:doc:`TableGen/index` description of the register file. .. _TargetInstrInfo: |