Minor wording tweak for memory model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136668 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 4 insertions, 4 deletions

diff --git a/docs/LangRef.html b/docs/LangRef.html
index b76a3d533c..6e77b4ac90 100644
--- a/docs/LangRef.html
+++ b/docs/LangRef.html
@@ -1555,10 +1555,10 @@ emit more than one instruction to read the series of bytes.</p>
 <p>Note that in cases where none of the atomic intrinsics are used, this model
 places only one restriction on IR transformations on top of what is required
 for single-threaded execution: introducing a store to a byte which might not
-otherwise be stored to can introduce undefined behavior.  (Specifically, in
-the case where another thread might write to and read from an address,
-introducing a store can change a load that may see exactly one write into
-a load that may see multiple writes.)</p>
+otherwise be stored is not allowed in general.  (Specifically, in the case
+where another thread might write to and read from an address, introducing a
+store can change a load that may see exactly one write into a load that may
+see multiple writes.)</p>
 
 <!-- FIXME: This model assumes all targets where concurrency is relevant have
 a byte-size store which doesn't affect adjacent bytes.  As far as I can tell,