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| author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2002-01-07 19:16:26 +0000 |
|---|---|---|
| committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2002-01-07 19:16:26 +0000 |
| commit | 42bd177eae30b6bdef578b6efb21e6c609aa5204 (patch) | |
| tree | f113d735eac3bf8c2be56e02c17761224714eacb /docs/RegisterAllocatorInfo.txt | |
| parent | 977fa8df93ac03b89ef07c94fa12ed7aec11f41c (diff) | |
| download | llvm-42bd177eae30b6bdef578b6efb21e6c609aa5204.tar.gz llvm-42bd177eae30b6bdef578b6efb21e6c609aa5204.tar.bz2 llvm-42bd177eae30b6bdef578b6efb21e6c609aa5204.tar.xz | |
Added comments, destructors where necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1491 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs/RegisterAllocatorInfo.txt')
| -rw-r--r-- | docs/RegisterAllocatorInfo.txt | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/docs/RegisterAllocatorInfo.txt b/docs/RegisterAllocatorInfo.txt index 557a2e597d..58a54505c1 100644 --- a/docs/RegisterAllocatorInfo.txt +++ b/docs/RegisterAllocatorInfo.txt @@ -34,7 +34,6 @@ Register allocation must be done as: 4. Input and Preconditions ========================== - Register allocation is done using machine instructions. The constructor to the class takes a pointer to a method, a target machine description and a live variable information for the method. @@ -50,6 +49,15 @@ The preconditions are: 5. Assumptions ============== + All variables (llvm Values) are defined before they are used. However, a + constant may not be defined in the machine instruction stream if it can be + used as an immediate value within a machine instruction. However, register + allocation does not have to worry about immediate constants since they + do not require registers. + + Since an llvm Value has a list of uses associated, it is sufficient to + record only the defs in a Live Range. + @@ -69,6 +77,11 @@ Registerallocation consists of the following main steps: All the above methods are called from PhyRegAlloc::allocateRegisters(). +All steps above except step 5 and suggesting colors in step 1 are indepenedent +of a particular target architecture. Targer independent code is availble in +../lib/CodeGen/RegAlloc. Target specific code for Sparc is available in +../lib/Target/Sparc. + 6.1. Construct Live-ranges & Suggest colors (machine specific) if required -------------------------------------------------------------------------- @@ -159,3 +172,11 @@ instructions that have been produced for that instruction by the register allocation (e.g., caller saving code) +7. Furture work +--------------- +If it is necessary to port the register allocator to another architecture +than Sparc, only the target specific code in ../lib/Target/Sparc needs to +be rewritten. Methods defined in class MachineRegInfo must be provided for +the new architecure. + +using ReservedColorList in RegClass
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