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| author | Eli Bendersky <eliben@google.com> | 2013-01-04 19:09:15 +0000 |
|---|---|---|
| committer | Eli Bendersky <eliben@google.com> | 2013-01-04 19:09:15 +0000 |
| commit | 7c88270ae2c7f7bbfba547220454aa08d4b64a8e (patch) | |
| tree | f9ce978dea94d98319efbac5ca45b7fc2c304951 /docs/TableGenFundamentals.rst | |
| parent | da704cc1e77d8314a7b116613d8f3a339aedbc19 (diff) | |
| download | llvm-7c88270ae2c7f7bbfba547220454aa08d4b64a8e.tar.gz llvm-7c88270ae2c7f7bbfba547220454aa08d4b64a8e.tar.bz2 llvm-7c88270ae2c7f7bbfba547220454aa08d4b64a8e.tar.xz | |
fix a couple of typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171508 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs/TableGenFundamentals.rst')
| -rw-r--r-- | docs/TableGenFundamentals.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/TableGenFundamentals.rst b/docs/TableGenFundamentals.rst index 356b7d208e..73bcd66a60 100644 --- a/docs/TableGenFundamentals.rst +++ b/docs/TableGenFundamentals.rst @@ -121,11 +121,11 @@ this (at the time of this writing): ... This definition corresponds to the 32-bit register-register ``add`` instruction -of the the x86 architecture. ``def ADD32rr`` defines a record named +of the x86 architecture. ``def ADD32rr`` defines a record named ``ADD32rr``, and the comment at the end of the line indicates the superclasses of the definition. The body of the record contains all of the data that TableGen assembled for the record, indicating that the instruction is part of -the "X86" namespace, the pattern indicating how the the instruction should be +the "X86" namespace, the pattern indicating how the instruction should be emitted into the assembly file, that it is a two-address instruction, has a particular encoding, etc. The contents and semantics of the information in the record are specific to the needs of the X86 backend, and are only shown as an |