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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-11-17 21:24:37 +0000 |
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| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-11-17 21:24:37 +0000 |
| commit | 0df7f51365f582afd755a832ea23a0b720f615b7 (patch) | |
| tree | 0d194c0b4aa731bdc056486451f0cc093d2f6834 /docs/WritingAnLLVMBackend.rst | |
| parent | 3bcf1e3bc038f2c349035914d79d62f6d30bb7d7 (diff) | |
| download | llvm-0df7f51365f582afd755a832ea23a0b720f615b7.tar.gz llvm-0df7f51365f582afd755a832ea23a0b720f615b7.tar.bz2 llvm-0df7f51365f582afd755a832ea23a0b720f615b7.tar.xz | |
Docs: Clearly separate Operand-related paragraphs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194977 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs/WritingAnLLVMBackend.rst')
| -rw-r--r-- | docs/WritingAnLLVMBackend.rst | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/docs/WritingAnLLVMBackend.rst b/docs/WritingAnLLVMBackend.rst index 0d29210f9a..5dd55d08ad 100644 --- a/docs/WritingAnLLVMBackend.rst +++ b/docs/WritingAnLLVMBackend.rst @@ -911,6 +911,9 @@ format instructions will bind the operands to the ``rd``, ``rs1``, and ``rs2`` fields. This results in the ``XNORrr`` instruction binding ``$dst``, ``$b``, and ``$c`` operands to the ``rd``, ``rs1``, and ``rs2`` fields respectively. +Instruction Operand Name Mapping +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + TableGen will also generate a function called getNamedOperandIdx() which can be used to look up an operand's index in a MachineInstr based on its TableGen name. Setting the UseNamedOperandTable bit in an instruction's @@ -952,6 +955,9 @@ XXXInstrInfo.h: int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); } // End namespace XXX +Instruction Scheduling +---------------------- + Instruction itineraries can be queried using MCDesc::getSchedClass(). The value can be named by an enumemation in llvm::XXX::Sched namespace generated by TableGen in XXXGenInstrInfo.inc. The name of the schedule classes are |