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| author | Weiming Zhao <weimingz@codeaurora.org> | 2014-01-15 01:32:12 +0000 |
|---|---|---|
| committer | Weiming Zhao <weimingz@codeaurora.org> | 2014-01-15 01:32:12 +0000 |
| commit | 2a0c41756bfb697f4c028b84501b31b1320786d1 (patch) | |
| tree | 44dfa356755cae4ea60667f995339e5f08e891f3 /docs | |
| parent | 0be7e6ffb1683c700d620376f318382e7a237cb2 (diff) | |
| download | llvm-2a0c41756bfb697f4c028b84501b31b1320786d1.tar.gz llvm-2a0c41756bfb697f4c028b84501b31b1320786d1.tar.bz2 llvm-2a0c41756bfb697f4c028b84501b31b1320786d1.tar.xz | |
PR 18466: Fix ARM Pseudo Expansion
When expanding neon pseudo stores, it may miss the implicit uses of sub
regs, which may cause post RA scheduler reorder instructions that
breakes anti dependency.
For example:
VST1d64QPseudo %R0<kill>, 16, %Q9_Q10, pred:14, pred:%noreg
will be expanded to
VST1d64Q %R0<kill>, 16, %D18, pred:14, pred:%noreg;
An instruction that defines %D20 may be scheduled before the store by
mistake.
This patches adds implicit uses for such case. For the example above, it
emits:
VST1d64Q %R0<kill>, 8, %D18, pred:14, pred:%noreg, %Q9_Q10<imp-use>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199282 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions