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| author | Alp Toker <alp@nuanti.com> | 2014-04-09 14:47:27 +0000 |
|---|---|---|
| committer | Alp Toker <alp@nuanti.com> | 2014-04-09 14:47:27 +0000 |
| commit | 46d36be2eb02f35fef15952699d0e32e6138760d (patch) | |
| tree | 377a6835c162218586f0bef2cf8f8c727ab9fc2a /docs | |
| parent | 35fb92daddc1322f8f1a1623f098eb6f28e0d149 (diff) | |
| download | llvm-46d36be2eb02f35fef15952699d0e32e6138760d.tar.gz llvm-46d36be2eb02f35fef15952699d0e32e6138760d.tar.bz2 llvm-46d36be2eb02f35fef15952699d0e32e6138760d.tar.xz | |
Fix some doc and comment typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205899 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/CompilerWriterInfo.rst | 2 | ||||
| -rw-r--r-- | docs/LangRef.rst | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/docs/CompilerWriterInfo.rst b/docs/CompilerWriterInfo.rst index 240271a1a4..606b5f5afe 100644 --- a/docs/CompilerWriterInfo.rst +++ b/docs/CompilerWriterInfo.rst @@ -113,7 +113,7 @@ XCore ----- * `The XMOS XS1 Architecture (ISA) <https://www.xmos.com/en/download/public/The-XMOS-XS1-Architecture%28X7879A%29.pdf>`_ -* `Tools Developement Guide (includes ABI) <https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf>`_ +* `Tools Development Guide (includes ABI) <https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf>`_ Other relevant lists -------------------- diff --git a/docs/LangRef.rst b/docs/LangRef.rst index fff627b8bb..752e357822 100644 --- a/docs/LangRef.rst +++ b/docs/LangRef.rst @@ -6969,7 +6969,7 @@ Semantics: On platforms with coherent instruction and data caches (e.g. x86), this intrinsic is a nop. On platforms with non-coherent instruction and data -cache (e.g. ARM, MIPS), the intrinsic is lowered either to appropiate +cache (e.g. ARM, MIPS), the intrinsic is lowered either to appropriate instructions or a system call, if cache flushing requires special privileges. |