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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-06 22:58:13 +0000 |
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| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-09-06 22:58:13 +0000 |
| commit | 8eb6719b1c13eadcb76d2249f2fcc5ff18de22e3 (patch) | |
| tree | 1356690523e668cdee49e7aaf49545cc03ca6391 /docs | |
| parent | 05bcca95e974a7120cd758770ea53363f903727a (diff) | |
| download | llvm-8eb6719b1c13eadcb76d2249f2fcc5ff18de22e3.tar.gz llvm-8eb6719b1c13eadcb76d2249f2fcc5ff18de22e3.tar.bz2 llvm-8eb6719b1c13eadcb76d2249f2fcc5ff18de22e3.tar.xz | |
How to write an LLVM backend, first draft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16203 91177308-0d34-0410-b5e6-96231b3b80d8
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| -rw-r--r-- | docs/WritingAnLLVMBackend.html | 245 |
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diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html new file mode 100644 index 0000000000..1fb88a3633 --- /dev/null +++ b/docs/WritingAnLLVMBackend.html @@ -0,0 +1,245 @@ +<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" + "http://www.w3.org/TR/html4/strict.dtd"> +<html> +<head> + <title>Writing an LLVM backend</title> + <link rel="stylesheet" href="llvm.css" type="text/css"> +</head> + +<body> + +<div class="doc_title"> + Writing an LLVM backend +</div> + +<ol> + <li><a href="#intro">Introduction</a> + <li><a href="#backends">Writing a backend</a> + <ol> + <li><a href="#machine">Machine backends</a></li> + <ol> + <li><a href="#machineTOC">Outline</a></li> + <li><a href="#machineDetails">Implementation details</a></li> + </ol></li> + <li><a href="#machine">Machine backends</a></li> + <li><a href="#lang">Language backends</a></li> + </ol></li> + <li><a href="#related">Related reading material</a> +</ol> + +<div class="doc_author"> + <p>Written by <a href="http://misha.brukman.net">Misha Brukman</a></p> +</div> + +<!-- *********************************************************************** --> +<div class="doc_section"> + <a name="intro">Introduction</a> +</div> +<!-- *********************************************************************** --> + +<div class="doc_text"> + +<p>This document describes techniques for writing backends for LLVM which +convert the LLVM representation to machine assembly code or other languages.</p> + +</div> + +<!-- *********************************************************************** --> +<div class="doc_section"> + <a name="backends">Writing a backend</a> +</div> +<!-- *********************************************************************** --> + +<!-- ======================================================================= --> +<div class="doc_subsection"> + <a name="machine">Machine backends</a> +</div> + +<!-- _______________________________________________________________________ --> +<div class="doc_subsubsection"> + <a name="machineTOC">Outline</a> +</div> + +<div class="doc_text"> + +<p>In general, you want to follow the format of X86 or PowerPC (in +<tt>lib/Target</tt>).</p> + +<p>To create a static compiler (one that emits text assembly), you need to +implement the following:</p> + +<ul> +<li>Describe the register set + <ul> + <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of + the register set and register classes</li> + <li>Implement a subclass of <tt><a + href="CodeGenerator.html#mregisterinfo">MRegisterInfo</a></tt></li> + </ul></li> +<li>Describe the instruction set + <ul> + <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of + the instruction set</li> + <li>Implement a subclass of <tt><a + href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></tt></li> + </ul></li> +<li>Describe the target machine + <ul> + <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of + the target that describes the pointer size and references the instruction + set</li> + <li>Implement a subclass of <tt><a + href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>, which + configures <tt><a href="CodeGenerator.html#targetdata">TargetData</a></tt> + correctly</li> + </ul></li> +<li>Implement the assembly printer for the architecture. Usually, if you have +described the instruction set with the assembly printer generator in mind, that +step can be almost automated.</li> +</ul> + +<p>Now, for static code generation you also need to write an instruction +selector for your platform: see <tt>lib/Target/*/*ISelSimple.cpp</tt> which +is no longer "simple" but it gives you the idea: you have to be able to create +MachineInstrs for any given LLVM instruction using the <tt>InstVisitor</tt> +pattern, and produce a <tt>MachineFunction</tt> with +<tt>MachineBasicBlock</tt>s full of <tt><a +href="CodeGenerator.html#machineinstr">MachineInstr</a></tt>s for a +corresponding LLVM Function. Creating an instruction selector is perhaps the +most time-consuming part of creating a back-end.</p> + +<p>To create a JIT for your platform:</p> + +<ul> +<li>Create a subclass of <tt><a + href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li> +<li>Create a machine code emitter that will be used to emit binary code + directly into memory, given <tt>MachineInstr</tt>s</li> +</ul> + +<p>Note that <tt>lib/target/Skeleton</tt> is a clean skeleton for a new target, +so you might want to start with that and adapt it for your target, and if you +are wondering how things are done, peek in the X86 or PowerPC target.</p> + +<p>The Skeleton target is non-functional but provides the basic building blocks +you will need for your endeavor.</p> + +</div> + +<!-- _______________________________________________________________________ --> +<div class="doc_subsubsection"> + <a name="machineDetails">Implementation details</a> +</div> + +<div class="doc_text"> + +<ul> + +<li><p><b>TableGen register info description</b> - describe a class which +will store the register's number in the binary encoding of the instruction +(e.g., for JIT purposes).</p> + +<p>You also need to define register classes to contain these registers, such as +the integer register class and floating-point register class, so that you can +allocate virtual registers to instructions from these sets, and let the +target-independent register allocator automatically choose the actual +architected registers.</p> + +<div class="doc_code"> +<pre> +// class Register is defined in Target.td +<b>class</b> <em>Target</em>Reg : Register { + <b>let</b> Namespace = "<em>Target</em>"; +} + +<b>class</b> IntReg<<b>bits</b><5> num> : <em>Target</em>Reg { + <b>field</b> <b>bits</b><5> Num = num; +} + +<b>def</b> R0 : IntReg<0>; +... + +// class RegisterClass is defined in Target.td +<b>def</b> IReg : RegisterClass<i64, 64, [R0, ... ]>; +</pre> +</div> +</li> + +<li><p><b>TableGen instruction info description</b> - break up instructions into +classes, usually that's already done by the manufacturer (see instruction +manual). Define a class for each instruction category. Define each opcode as a +subclass of the category, with appropriate parameters such as the fixed binary +encoding of opcodes and extended opcodes, and map the register bits to the bits +of the instruction which they are encoded in (for the JIT). Also specify how +the instruction should be printed so it can use the automatic assembly printer, +e.g.:</p> + +<div class="doc_code"> +<pre> +// class Instruction is defined in Target.td +<b>class</b> Form<<b>bits</b><6> opcode, <b>dag</b> OL, <b>string</b> asmstr> : Instruction { + <b>field</b> <b>bits</b><42> Inst; + + <b>let</b> Namespace = "<em>Target</em>"; + <b>let</b> Inst{0-6} = opcode; + <b>let</b> OperandList = OL; + <b>let</b> AsmString = asmstr; +} + +<b>def</b> ADD : Form<42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB">; +</pre> +</div> +</li> + +</ul> + +</div> + +<!-- ======================================================================= --> +<div class="doc_subsection"> + <a name="lang">Language backends</a> +</div> + +<div class="doc_text"> + +<p>For now, just take a look at <tt>lib/Target/CBackend</tt> for an example of +how the C backend is written.</p> + +</div> + +<!-- *********************************************************************** --> +<div class="doc_section"> + <a name="related">Related reading material</a> +</div> +<!-- *********************************************************************** --> + +<div class="doc_text"> + +<ul> +<li><a href="CodeGenerator.html">Code generator</a> - + describes some of the classes in code generation at a high level, but + it is not (yet) complete.</li> +<li><a href="TableGenFundamentals.html">TableGen fundamentals</a> - + describes how to use TableGen to describe your target information succinctly +</li> +</ul> + +</div> + +<!-- *********************************************************************** --> + +<hr> +<address> + <a href="http://jigsaw.w3.org/css-validator/check/referer"><img + src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"></a> + <a href="http://validator.w3.org/check/referer"><img + src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a> + + <a href="http://misha.brukman.net">Misha Brukman</a><br> + <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a> + <br> + Last modified: $Date$ +</address> + +</body> +</html> |