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authorManman Ren <mren@apple.com>2012-06-01 19:33:18 +0000
committerManman Ren <mren@apple.com>2012-06-01 19:33:18 +0000
commit68f25571e759c1fcf2da206109647259f49f7416 (patch)
tree861c26c6230399c7a15e25af8e868f16aafb9ad2 /include/llvm/CodeGen/FastISel.h
parenta0c5e6ceb53c0f77906d813a354b19e72d26950c (diff)
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ARM: properly handle alignment for struct byval.
Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157830 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/FastISel.h')
-rw-r--r--include/llvm/CodeGen/FastISel.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index e57c8b18c6..9fe743eddb 100644
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -299,6 +299,15 @@ protected:
unsigned Op1, bool Op1IsKill,
uint64_t Imm);
+ /// FastEmitInst_rrii - Emit a MachineInstr with two register operands,
+ /// two immediates operands, and a result register in the given register
+ /// class.
+ unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
+ const TargetRegisterClass *RC,
+ unsigned Op0, bool Op0IsKill,
+ unsigned Op1, bool Op1IsKill,
+ uint64_t Imm1, uint64_t Imm2);
+
/// FastEmitInst_i - Emit a MachineInstr with a single immediate
/// operand, and a result register in the given register class.
unsigned FastEmitInst_i(unsigned MachineInstrOpcode,