TargetPassConfig: confine the MC configuration to TargetMachine.

Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.

Sorry for the target header churn. Attempting to stabilize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 29 insertions, 16 deletions

diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 308026dd86..30abcd7b92 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -35,18 +35,17 @@ namespace llvm {
 ///
 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
 /// to the internals of other CodeGen passes.
-///
-/// FIXME: Why are we passing the DisableVerify flags around instead of setting
-/// an options in the target machine, like all the other driver options?
 class TargetPassConfig : public ImmutablePass {
 protected:
   TargetMachine *TM;
   PassManagerBase ±
+
+  // Target Pass Options
+  //
   bool DisableVerify;
 
 public:
-  TargetPassConfig(TargetMachine *tm, PassManagerBase &pm,
-                   bool DisableVerifyFlag);
+  TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
   // Dummy constructor.
   TargetPassConfig();
 
@@ -59,17 +58,37 @@ public:
     return *static_cast<TMC*>(TM);
   }
 
+  const TargetLowering *getTargetLowering() const {
+    return TM->getTargetLowering();
+  }
+
   CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
 
-  const TargetLowering *getTargetLowering() const { return TM->getTargetLowering(); }
+  void setDisableVerify(bool disable) { DisableVerify = disable; }
+
+  /// Add common target configurable passes that perform LLVM IR to IR
+  /// transforms following machine independent optimization.
+  virtual void addIRPasses();
+
+  /// Add common passes that perform LLVM IR to IR transforms in preparation for
+  /// instruction selection.
+  virtual void addISelPrepare();
+
+  /// addInstSelector - This method should install an instruction selector pass,
+  /// which converts from LLVM code to machine instructions.
+  virtual bool addInstSelector() {
+    return true;
+  }
 
   /// Add the complete, standard set of LLVM CodeGen passes.
   /// Fully developed targets will not generally override this.
-  virtual bool addCodeGenPasses(MCContext *&OutContext);
-
+  virtual void addMachinePasses();
 protected:
-  /// Convenient points in the common codegen pass pipeline for inserting
-  /// passes, and major CodeGen stages that some targets may override.
+  /// Methods with trivial inline returns are convenient points in the common
+  /// codegen pass pipeline where targets may insert passes. Methods with
+  /// out-of-line standard implementations are major CodeGen stages called by
+  /// addMachinePasses. Some targets may override major stages when inserting
+  /// passes is insufficient, but maintaining overriden stages is more work.
   ///
 
   /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
@@ -78,12 +97,6 @@ protected:
     return true;
   }
 
-  /// addInstSelector - This method should install an instruction selector pass,
-  /// which converts from LLVM code to machine instructions.
-  virtual bool addInstSelector() {
-    return true;
-  }
-
   /// addPreRegAlloc - This method may be implemented by targets that want to
   /// run passes immediately before register allocation. This should return
   /// true if -print-machineinstrs should print after these passes.