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author | Evan Cheng <evan.cheng@apple.com> | 2006-05-12 01:58:24 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2006-05-12 01:58:24 +0000 |
commit | 13d41b9d721f98372b97d2ec119e6c91932ab0ae (patch) | |
tree | b6068fb8e9346f9e69de380ca3ce9bc4f5e0a8a4 /include/llvm/CodeGen/ScheduleDAG.h | |
parent | 31ff1ff348bce63f5d802530c5a99f6a4d6db104 (diff) | |
download | llvm-13d41b9d721f98372b97d2ec119e6c91932ab0ae.tar.gz llvm-13d41b9d721f98372b97d2ec119e6c91932ab0ae.tar.bz2 llvm-13d41b9d721f98372b97d2ec119e6c91932ab0ae.tar.xz |
Add capability to scheduler to commute nodes for profit.
If a two-address code whose first operand has uses below, it should be commuted
when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28230 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/ScheduleDAG.h')
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 5f9236d401..6263dfb57f 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -91,7 +91,7 @@ namespace llvm { short NumChainPredsLeft; // # of chain preds not scheduled. short NumChainSuccsLeft; // # of chain succs not scheduled. bool isTwoAddress : 1; // Is a two-address instruction. - bool isDefNUseOperand : 1; // Is a def&use operand. + bool isCommutable : 1; // Is a commutable instruction. bool isPending : 1; // True once pending. bool isAvailable : 1; // True once available. bool isScheduled : 1; // True once scheduled. @@ -105,7 +105,7 @@ namespace llvm { SUnit(SDNode *node, unsigned nodenum) : Node(node), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), NumChainPredsLeft(0), NumChainSuccsLeft(0), - isTwoAddress(false), isDefNUseOperand(false), + isTwoAddress(false), isCommutable(false), isPending(false), isAvailable(false), isScheduled(false), Latency(0), CycleBound(0), Cycle(0), Depth(0), Height(0), NodeNum(nodenum) {} @@ -162,10 +162,11 @@ namespace llvm { const MRegisterInfo *MRI; // Target processor register info SSARegMap *RegMap; // Virtual/real register map MachineConstantPool *ConstPool; // Target constant pool - std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s represent - // noop instructions. + std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s + // represent noop instructions. std::map<SDNode*, SUnit*> SUnitMap; // SDNode to SUnit mapping (n -> 1). std::vector<SUnit> SUnits; // The scheduling units. + std::set<SDNode*> CommuteSet; // Nodes the should be commuted. ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, const TargetMachine &tm) |