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author | Chris Lattner <sabre@nondot.org> | 2006-03-10 07:48:52 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-03-10 07:48:52 +0000 |
commit | 37cb415eec53e20ed77c1c90f86310de217f3e6c (patch) | |
tree | 577a5156bf75f519b6f3270de2e6d12de7d928b9 /include/llvm/CodeGen/ScheduleDAG.h | |
parent | 2f5806c2b37a4e59cb12a6d49f0e3423c2082a64 (diff) | |
download | llvm-37cb415eec53e20ed77c1c90f86310de217f3e6c.tar.gz llvm-37cb415eec53e20ed77c1c90f86310de217f3e6c.tar.bz2 llvm-37cb415eec53e20ed77c1c90f86310de217f3e6c.tar.xz |
Simplify the interface to the schedulers, to not pass the selected heuristic
in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26691 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/ScheduleDAG.h')
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 18 |
1 files changed, 4 insertions, 14 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 9c948a61f1..ba3637b5c3 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -34,16 +34,6 @@ namespace llvm { typedef std::vector<NodeInfoPtr> NIVector; typedef std::vector<NodeInfoPtr>::iterator NIIterator; - // Scheduling heuristics - enum SchedHeuristics { - defaultScheduling, // Let the target specify its preference. - noScheduling, // No scheduling, emit breadth first sequence. - simpleScheduling, // Two pass, min. critical path, max. utilization. - simpleNoItinScheduling, // Same as above exact using generic latency. - listSchedulingBURR, // Bottom up reg reduction list scheduling. - listSchedulingTD // Top-down list scheduler. - }; - /// HazardRecognizer - This determines whether or not an instruction can be /// issued this cycle, and whether or not a noop needs to be inserted to handle /// the hazard. @@ -296,8 +286,7 @@ namespace llvm { const TargetMachine &tm) : DAG(dag), BB(bb), TM(tm) {} - virtual ~ScheduleDAG() { - }; + virtual ~ScheduleDAG() {} /// Run - perform scheduling. /// @@ -337,10 +326,11 @@ namespace llvm { std::map<SDNode*, unsigned> &VRBaseMap); }; + ScheduleDAG *createBFS_DAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB); + /// createSimpleDAGScheduler - This creates a simple two pass instruction /// scheduler. - ScheduleDAG* createSimpleDAGScheduler(SchedHeuristics Heuristic, - SelectionDAG &DAG, + ScheduleDAG* createSimpleDAGScheduler(bool NoItins, SelectionDAG &DAG, MachineBasicBlock *BB); /// createBURRListDAGScheduler - This creates a bottom up register usage |