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authorAndrew Trick <atrick@apple.com>2012-02-01 22:13:57 +0000
committerAndrew Trick <atrick@apple.com>2012-02-01 22:13:57 +0000
commitee498d3254b86bceb4f441741e9f442990647ce6 (patch)
treef2319c428f9e572162a0ca172a573da5ea39bcdf /include/llvm/CodeGen/SchedulerRegistry.h
parentf18a9a2314542ad3b7a601b86969073519e19b0d (diff)
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VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/SchedulerRegistry.h')
-rw-r--r--include/llvm/CodeGen/SchedulerRegistry.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index 3af6fcfcb6..a582b0c40c 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -42,7 +42,7 @@ public:
: MachinePassRegistryNode(N, D, (MachinePassCtor)C)
{ Registry.Add(this); }
~RegisterScheduler() { Registry.Remove(this); }
-
+
// Accessors.
//
@@ -92,6 +92,11 @@ ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel);
+/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
+/// DFA driven list scheduler with clustering heuristic to control
+/// register pressure.
+ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
+ CodeGenOpt::Level OptLevel);
/// createDefaultScheduler - This creates an instruction scheduler appropriate
/// for the target.
ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,