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| author | Andrew Trick <atrick@apple.com> | 2012-10-09 23:44:26 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-10-09 23:44:26 +0000 |
| commit | 42bb106118db51393c2524c8b0c7f7ba6674cfd7 (patch) | |
| tree | 4db8fd8567db1de98c4e5e5b6761152b52e94c77 /include/llvm/CodeGen/TargetSchedule.h | |
| parent | 714973e459d6611dd3e67f77968aba55528664b4 (diff) | |
| download | llvm-42bb106118db51393c2524c8b0c7f7ba6674cfd7.tar.gz llvm-42bb106118db51393c2524c8b0c7f7ba6674cfd7.tar.bz2 llvm-42bb106118db51393c2524c8b0c7f7ba6674cfd7.tar.xz | |
misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/TargetSchedule.h')
| -rw-r--r-- | include/llvm/CodeGen/TargetSchedule.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/llvm/CodeGen/TargetSchedule.h b/include/llvm/CodeGen/TargetSchedule.h index 541ee66c0c..ffcb793fc6 100644 --- a/include/llvm/CodeGen/TargetSchedule.h +++ b/include/llvm/CodeGen/TargetSchedule.h @@ -45,11 +45,11 @@ public: /// Return true if this machine model includes an instruction-level scheduling /// model. This is more detailed than the course grain IssueWidth and default /// latency properties, but separate from the per-cycle itinerary data. - bool hasInstrSchedModel() const { return SchedModel.hasInstrSchedModel(); } + bool hasInstrSchedModel() const; /// Return true if this machine model includes cycle-to-cycle itinerary /// data. This models scheduling at each stage in the processor pipeline. - bool hasInstrItineraries() const { return !InstrItins.isEmpty(); } + bool hasInstrItineraries() const; /// computeOperandLatency - Compute and return the latency of the given data /// dependent def and use when the operand indices are already known. UseMI |