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author | Evan Cheng <evan.cheng@apple.com> | 2006-10-17 21:12:56 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2006-10-17 21:12:56 +0000 |
commit | 35acd30a2e96a5a4ad9fa837971af2cc583bcd1f (patch) | |
tree | bb26454b95870fec36683c75efce04d1ee3ed0ca /include/llvm/CodeGen | |
parent | 226f8bc38c7d1916518602126c7091812265bf6b (diff) | |
download | llvm-35acd30a2e96a5a4ad9fa837971af2cc583bcd1f.tar.gz llvm-35acd30a2e96a5a4ad9fa837971af2cc583bcd1f.tar.bz2 llvm-35acd30a2e96a5a4ad9fa837971af2cc583bcd1f.tar.xz |
Split PRE_INDEXED to PRE_INC / PRE_DEC and similarly for POST_INDEXED.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31015 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen')
-rw-r--r-- | include/llvm/CodeGen/SelectionDAG.h | 1 | ||||
-rw-r--r-- | include/llvm/CodeGen/SelectionDAGNodes.h | 21 |
2 files changed, 14 insertions, 8 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 144b9d5eaa..05971d2ba0 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -314,6 +314,7 @@ public: SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, const Value *SV, int SVOffset, MVT::ValueType EVT, bool isVolatile=false); + SDOperand getPreIndexedLoad(SDOperand OrigLoad, SDOperand Base); SDOperand getVecLoad(unsigned Count, MVT::ValueType VT, SDOperand Chain, SDOperand Ptr, SDOperand SV); diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index dea371e889..c06172a612 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -528,8 +528,8 @@ namespace ISD { /// chain, an unindexed load produces one value (result of the /// load); an unindexed store does not produces a value. /// - /// PRE_INDEXED Similar to the unindexed mode where the effective address is - /// the result of computation of the base pointer. However, it + /// PRE_INC Similar to the unindexed mode where the effective address is + /// PRE_DEC the result of computation of the base pointer. However, it /// considers the computation as being folded into the load / /// store operation (i.e. the load / store does the address /// computation as well as performing the memory transaction). @@ -539,8 +539,8 @@ namespace ISD { /// computation); a pre-indexed store produces one value (result /// of the address computation). /// - /// POST_INDEXED The effective address is the value of the base pointer. The - /// value of the offset operand is then added to the base after + /// POST_INC The effective address is the value of the base pointer. The + /// POST_DEC value of the offset operand is then added to the base after /// memory transaction. In addition to producing a chain, /// post-indexed load produces two values (the result of the load /// and the result of the base + offset computation); a @@ -549,8 +549,10 @@ namespace ISD { /// enum MemOpAddrMode { UNINDEXED = 0, - PRE_INDEXED, - POST_INDEXED + PRE_INC, + PRE_DEC, + POST_INC, + POST_DEC }; //===--------------------------------------------------------------------===// @@ -854,6 +856,7 @@ public: /// getOperationName - Return the opcode of this operation for printing. /// const char* getOperationName(const SelectionDAG *G = 0) const; + static const char* getAddressingModeName(ISD::MemOpAddrMode AM); void dump() const; void dump(const SelectionDAG *G) const; @@ -1405,7 +1408,8 @@ protected: : SDNode(ISD::LOAD, Chain, Ptr, Off), AddrMode(AM), ExtType(ETy), LoadedVT(LVT), SrcValue(SV), SVOffset(O), Alignment(Align), IsVolatile(Vol) { - assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) && + assert((Off.getOpcode() == ISD::UNDEF || + AddrMode == ISD::POST_INC || AddrMode == ISD::POST_DEC) && "Only post-indexed load has a non-undef offset operand"); } public: @@ -1458,7 +1462,8 @@ protected: : SDNode(ISD::STORE, Chain, Value, Ptr, Off), AddrMode(AM), IsTruncStore(isTrunc), StoredVT(SVT), SrcValue(SV), SVOffset(O), Alignment(Align), IsVolatile(Vol) { - assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) && + assert((Off.getOpcode() == ISD::UNDEF || + AddrMode == ISD::POST_INC || AddrMode == ISD::POST_DEC) && "Only post-indexed store has a non-undef offset operand"); } public: |