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authorAndrew Trick <atrick@apple.com>2012-10-09 23:44:29 +0000
committerAndrew Trick <atrick@apple.com>2012-10-09 23:44:29 +0000
commitc92d72abd03b0c29099b3f87f4cb67a299610f03 (patch)
tree1045fc43def9d876e5e60d663e0a78712d1e913f /include/llvm/CodeGen
parent42bb106118db51393c2524c8b0c7f7ba6674cfd7 (diff)
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misched: Doxument the TargetSchedule API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165565 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen')
-rw-r--r--include/llvm/CodeGen/TargetSchedule.h29
1 files changed, 22 insertions, 7 deletions
diff --git a/include/llvm/CodeGen/TargetSchedule.h b/include/llvm/CodeGen/TargetSchedule.h
index ffcb793fc6..6a5359de14 100644
--- a/include/llvm/CodeGen/TargetSchedule.h
+++ b/include/llvm/CodeGen/TargetSchedule.h
@@ -37,23 +37,35 @@ class TargetSchedModel {
public:
TargetSchedModel(): STI(0), TII(0) {}
+ /// \brief Initialize the machine model for instruction scheduling.
+ ///
+ /// The machine model API keeps a copy of the top-level MCSchedModel table
+ /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
+ /// dynamic properties.
void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
const TargetInstrInfo *tii);
+ /// \brief TargetInstrInfo getter.
const TargetInstrInfo *getInstrInfo() const { return TII; }
- /// Return true if this machine model includes an instruction-level scheduling
- /// model. This is more detailed than the course grain IssueWidth and default
+ /// \brief Return true if this machine model includes an instruction-level
+ /// scheduling model.
+ ///
+ /// This is more detailed than the course grain IssueWidth and default
/// latency properties, but separate from the per-cycle itinerary data.
bool hasInstrSchedModel() const;
- /// Return true if this machine model includes cycle-to-cycle itinerary
- /// data. This models scheduling at each stage in the processor pipeline.
+ /// \brief Return true if this machine model includes cycle-to-cycle itinerary
+ /// data.
+ ///
+ /// This models scheduling at each stage in the processor pipeline.
bool hasInstrItineraries() const;
- /// computeOperandLatency - Compute and return the latency of the given data
- /// dependent def and use when the operand indices are already known. UseMI
- /// may be NULL for an unknown user.
+ /// \brief Compute operand latency based on the available machine model.
+ ///
+ /// Computes and return the latency of the given data dependent def and use
+ /// when the operand indices are already known. UseMI may be NULL for an
+ /// unknown user.
///
/// FindMin may be set to get the minimum vs. expected latency. Minimum
/// latency is used for scheduling groups, while expected latency is for
@@ -62,7 +74,10 @@ public:
const MachineInstr *UseMI, unsigned UseOperIdx,
bool FindMin) const;
+ /// \brief Identify the processor corresponding to the current subtarget.
unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
+
+ /// \brief Maximum number of micro-ops that may be scheduled per cycle.
unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
private: