AArch64: add initial NEON support

Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 41 insertions, 0 deletions

diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td
new file mode 100644
index 0000000000..d7b1947db1
--- /dev/null
+++ b/include/llvm/IR/IntrinsicsAArch64.td
@@ -0,0 +1,41 @@
+//===- IntrinsicsAArch64.td - Defines AArch64 intrinsics -----------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the AArch64-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Advanced SIMD (NEON)
+
+let TargetPrefix = "aarch64" in {  // All intrinsics start with "llvm.aarch64.".
+
+// Vector Absolute Compare (Floating Point)
+def int_aarch64_neon_vacgeq : Intrinsic<[llvm_v2i64_ty],
+                                    [llvm_v2f64_ty, llvm_v2f64_ty],
+                                    [IntrNoMem]>;
+def int_aarch64_neon_vacgtq : Intrinsic<[llvm_v2i64_ty],
+                                    [llvm_v2f64_ty, llvm_v2f64_ty],
+                                    [IntrNoMem]>;
+
+// Vector maxNum (Floating Point)
+def int_aarch64_neon_vmaxnm : Neon_2Arg_Intrinsic;
+
+// Vector minNum (Floating Point)
+def int_aarch64_neon_vminnm : Neon_2Arg_Intrinsic;
+
+// Vector Pairwise maxNum (Floating Point)
+def int_aarch64_neon_vpmaxnm : Neon_2Arg_Intrinsic;
+
+// Vector Pairwise minNum (Floating Point)
+def int_aarch64_neon_vpminnm : Neon_2Arg_Intrinsic;
+
+// Vector Multiply Extended (Floating Point)
+def int_aarch64_neon_vmulx : Neon_2Arg_Intrinsic;
+}