diff options
| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-20 08:38:21 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-20 08:38:21 +0000 |
| commit | c149fbbe279ef623e6067304fd08dc1a62d74f7d (patch) | |
| tree | 0503e43c0d1724f334bcc615ced3cd498f3deeca /include/llvm/IR/IntrinsicsMips.td | |
| parent | 3480d1b84e0bdea91c08dcd931fe86b562971f3d (diff) | |
| download | llvm-c149fbbe279ef623e6067304fd08dc1a62d74f7d.tar.gz llvm-c149fbbe279ef623e6067304fd08dc1a62d74f7d.tar.bz2 llvm-c149fbbe279ef623e6067304fd08dc1a62d74f7d.tar.xz | |
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/IR/IntrinsicsMips.td')
| -rw-r--r-- | include/llvm/IR/IntrinsicsMips.td | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td index 0c413dcdb1..9e6d202d7a 100644 --- a/include/llvm/IR/IntrinsicsMips.td +++ b/include/llvm/IR/IntrinsicsMips.td @@ -447,6 +447,9 @@ def int_mips_addvi_w : GCCBuiltin<"__builtin_msa_addvi_w">, def int_mips_addvi_d : GCCBuiltin<"__builtin_msa_addvi_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [Commutative]>; +def int_mips_and_v : GCCBuiltin<"__builtin_msa_and_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_andi_b : GCCBuiltin<"__builtin_msa_andi_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; @@ -558,9 +561,15 @@ def int_mips_binsri_w : GCCBuiltin<"__builtin_msa_binsri_w">, def int_mips_binsri_d : GCCBuiltin<"__builtin_msa_binsri_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], []>; +def int_mips_bmnz_v : GCCBuiltin<"__builtin_msa_bmnz_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_bmnzi_b : GCCBuiltin<"__builtin_msa_bmnzi_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; +def int_mips_bmz_v : GCCBuiltin<"__builtin_msa_bmz_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_bmzi_b : GCCBuiltin<"__builtin_msa_bmzi_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; @@ -582,6 +591,9 @@ def int_mips_bnegi_w : GCCBuiltin<"__builtin_msa_bnegi_w">, def int_mips_bnegi_d : GCCBuiltin<"__builtin_msa_bnegi_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], []>; +def int_mips_bsel_v : GCCBuiltin<"__builtin_msa_bsel_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_bseli_b : GCCBuiltin<"__builtin_msa_bseli_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; def int_mips_bseli_h : GCCBuiltin<"__builtin_msa_bseli_h">, @@ -1219,9 +1231,15 @@ def int_mips_nlzc_w : GCCBuiltin<"__builtin_msa_nlzc_w">, def int_mips_nlzc_d : GCCBuiltin<"__builtin_msa_nlzc_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], []>; +def int_mips_nor_v : GCCBuiltin<"__builtin_msa_nor_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_nori_b : GCCBuiltin<"__builtin_msa_nori_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; +def int_mips_or_v : GCCBuiltin<"__builtin_msa_or_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_ori_b : GCCBuiltin<"__builtin_msa_ori_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; @@ -1430,6 +1448,9 @@ def int_mips_vshf_w : GCCBuiltin<"__builtin_msa_vshf_w">, def int_mips_vshf_d : GCCBuiltin<"__builtin_msa_vshf_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [Commutative]>; +def int_mips_xor_v : GCCBuiltin<"__builtin_msa_xor_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], []>; + def int_mips_xori_b : GCCBuiltin<"__builtin_msa_xori_b">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], []>; } |