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| author | Tim Northover <tnorthover@apple.com> | 2014-02-26 11:55:09 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-02-26 11:55:09 +0000 |
| commit | 530869f8bcd9d28acebc7836ecc022d98fcff9e2 (patch) | |
| tree | 0e68f403f42165b89a16c07f3bdadce1b0052d31 /include/llvm/IR | |
| parent | e7082383732df492d8fabd17c31300db08de7627 (diff) | |
| download | llvm-530869f8bcd9d28acebc7836ecc022d98fcff9e2.tar.gz llvm-530869f8bcd9d28acebc7836ecc022d98fcff9e2.tar.bz2 llvm-530869f8bcd9d28acebc7836ecc022d98fcff9e2.tar.xz | |
AArch64: simplify tbl/tbx polymorphism
The table argument is always 128-bit (and interpreted as <16 x i8>) so the
extra specifier for it is just clutter.
No user-visible behaviour change, so no tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202258 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/IR')
| -rw-r--r-- | include/llvm/IR/IntrinsicsAArch64.td | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/include/llvm/IR/IntrinsicsAArch64.td b/include/llvm/IR/IntrinsicsAArch64.td index bb84b142ed..c052963bf9 100644 --- a/include/llvm/IR/IntrinsicsAArch64.td +++ b/include/llvm/IR/IntrinsicsAArch64.td @@ -110,22 +110,22 @@ def int_aarch64_neon_vminnmv : // Vector Table Lookup. def int_aarch64_neon_vtbl1 : Intrinsic<[llvm_anyvector_ty], - [llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; + [llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; def int_aarch64_neon_vtbl2 : Intrinsic<[llvm_anyvector_ty], - [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<0>], + [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; def int_aarch64_neon_vtbl3 : Intrinsic<[llvm_anyvector_ty], - [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, + [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; def int_aarch64_neon_vtbl4 : Intrinsic<[llvm_anyvector_ty], - [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, - LLVMMatchType<1>, LLVMMatchType<0>], [IntrNoMem]>; + [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; // Vector Table Extension. // Some elements of the destination vector may not be updated, so the original @@ -133,23 +133,23 @@ def int_aarch64_neon_vtbl4 : // arguments after that are the table. def int_aarch64_neon_vtbx1 : Intrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], + [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; def int_aarch64_neon_vtbx2 : Intrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>, - LLVMMatchType<0>], [IntrNoMem]>; + [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, + LLVMMatchType<0>], [IntrNoMem]>; def int_aarch64_neon_vtbx3 : Intrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>, - LLVMMatchType<1>, LLVMMatchType<0>], [IntrNoMem]>; + [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; def int_aarch64_neon_vtbx4 : Intrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>, - LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<0>], + [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, + llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; // Vector Load/store |