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author | Dale Johannesen <dalej@apple.com> | 2010-09-01 22:43:48 +0000 |
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committer | Dale Johannesen <dalej@apple.com> | 2010-09-01 22:43:48 +0000 |
commit | 97511ceffa47d71c805b58143a24c78cdba2a5c1 (patch) | |
tree | da6e3920ba729a56eca38d67b664623649a84695 /include/llvm/IntrinsicsX86.td | |
parent | 29c353b9c3d8094b9ac7cbbc23cfc8d23a010db4 (diff) | |
download | llvm-97511ceffa47d71c805b58143a24c78cdba2a5c1.tar.gz llvm-97511ceffa47d71c805b58143a24c78cdba2a5c1.tar.bz2 llvm-97511ceffa47d71c805b58143a24c78cdba2a5c1.tar.xz |
Recommit with changes. Comment out palignr for the
moment, as there's a testcase that uses it and expects it
to be subject to optimizations; we won't be doing that.
Some adjustments based on feedback from Bill.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/IntrinsicsX86.td')
-rw-r--r-- | include/llvm/IntrinsicsX86.td | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td index ced5d8e00d..b06fe33616 100644 --- a/include/llvm/IntrinsicsX86.td +++ b/include/llvm/IntrinsicsX86.td @@ -630,6 +630,9 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_ssse3_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], + [IntrNoMem]>; } // Sign ops @@ -1567,12 +1570,20 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; - def int_x86_mmx_cvtsi32_MMX : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, +// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, +// Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, +// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_mmx_pextr_w : + Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], + [IntrNoMem]>; + + def int_x86_mmx_pinsr_w : + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, + llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + + def int_x86_mmx_cvtsi32_si64 : Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; - def int_x86_mmx_cvtsi64_MMX : - Intrinsic<[llvm_v1i64_ty], [llvm_i64_ty], [IntrNoMem]>; - def int_x86_mmx_MMX_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, + def int_x86_mmx_cvtsi64_si32 : Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_MMX_si64 : - Intrinsic<[llvm_i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; } |