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| author | Silviu Baranga <silviu.baranga@arm.com> | 2013-01-25 10:39:49 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2013-01-25 10:39:49 +0000 |
| commit | 4a9256f265a7fcccd1f04518b55fd751f3a920a8 (patch) | |
| tree | d061106e49ed71c03aac18de8a456782e9486a93 /include/llvm/TableGen | |
| parent | a3bb665c6505ff78c29a37ca95dad1d297928791 (diff) | |
| download | llvm-4a9256f265a7fcccd1f04518b55fd751f3a920a8.tar.gz llvm-4a9256f265a7fcccd1f04518b55fd751f3a920a8.tar.bz2 llvm-4a9256f265a7fcccd1f04518b55fd751f3a920a8.tar.xz | |
Fixed the condition codes for the atomic64 min/umin code generation on ARM. If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/TableGen')
0 files changed, 0 insertions, 0 deletions