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author | Andrew Trick <atrick@apple.com> | 2013-05-25 02:42:55 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-05-25 02:42:55 +0000 |
commit | ac6d9bec671252dd1e596fa71180ff6b39d06b5d (patch) | |
tree | 414f60df511ae112e9498df4f722cb1a9ee2fbba /include/llvm/Target | |
parent | ea5db0c315f1ab8ee3be52e0e765c32d3efff024 (diff) | |
download | llvm-ac6d9bec671252dd1e596fa71180ff6b39d06b5d.tar.gz llvm-ac6d9bec671252dd1e596fa71180ff6b39d06b5d.tar.bz2 llvm-ac6d9bec671252dd1e596fa71180ff6b39d06b5d.tar.xz |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target')
-rw-r--r-- | include/llvm/Target/TargetLowering.h | 21 | ||||
-rw-r--r-- | include/llvm/Target/TargetSelectionDAGInfo.h | 6 |
2 files changed, 13 insertions, 14 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 2bad48b33d..41a4a2b838 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -30,7 +30,6 @@ #include "llvm/IR/CallingConv.h" #include "llvm/IR/InlineAsm.h" #include "llvm/Support/CallSite.h" -#include "llvm/Support/DebugLoc.h" #include "llvm/Target/TargetCallingConv.h" #include "llvm/Target/TargetMachine.h" #include <climits> @@ -1717,11 +1716,11 @@ public: void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode, DebugLoc DL) const; + ISD::CondCode &CCCode, SDLoc DL) const; SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, - bool isSigned, DebugLoc dl) const; + bool isSigned, SDLoc dl) const; //===--------------------------------------------------------------------===// // TargetLowering Optimization Methods @@ -1761,7 +1760,7 @@ public: /// cast, but it could be generalized for targets with other types of /// implicit widening casts. bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, - DebugLoc dl); + SDLoc dl); }; /// SimplifyDemandedBits - Look at Op. At this point, we know that only the @@ -1823,7 +1822,7 @@ public: /// and cc. If it is unable to simplify it, return a null SDValue. SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, - DAGCombinerInfo &DCI, DebugLoc dl) const; + DAGCombinerInfo &DCI, SDLoc dl) const; /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the /// node is a GlobalAddress + offset. @@ -1884,7 +1883,7 @@ public: LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/, const SmallVectorImpl<ISD::InputArg> &/*Ins*/, - DebugLoc /*dl*/, SelectionDAG &/*DAG*/, + SDLoc /*dl*/, SelectionDAG &/*DAG*/, SmallVectorImpl<SDValue> &/*InVals*/) const { llvm_unreachable("Not Implemented"); } @@ -1930,7 +1929,7 @@ public: SDValue Callee; ArgListTy &Args; SelectionDAG &DAG; - DebugLoc DL; + SDLoc DL; ImmutableCallSite *CS; SmallVector<ISD::OutputArg, 32> Outs; SmallVector<SDValue, 32> OutVals; @@ -1941,7 +1940,7 @@ public: /// ImmutableCallSite \p cs. CallLoweringInfo(SDValue chain, Type *retTy, FunctionType *FTy, bool isTailCall, SDValue callee, - ArgListTy &args, SelectionDAG &dag, DebugLoc dl, + ArgListTy &args, SelectionDAG &dag, SDLoc dl, ImmutableCallSite &cs) : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)), RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()), @@ -1958,7 +1957,7 @@ public: bool isVarArg, bool isInReg, unsigned numFixedArgs, CallingConv::ID callConv, bool isTailCall, bool doesNotReturn, bool isReturnValueUsed, SDValue callee, - ArgListTy &args, SelectionDAG &dag, DebugLoc dl) + ArgListTy &args, SelectionDAG &dag, SDLoc dl) : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt), IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn), IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall), @@ -2011,7 +2010,7 @@ public: bool /*isVarArg*/, const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, const SmallVectorImpl<SDValue> &/*OutVals*/, - DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const { + SDLoc /*dl*/, SelectionDAG &/*DAG*/) const { llvm_unreachable("Not Implemented"); } @@ -2235,7 +2234,7 @@ public: //===--------------------------------------------------------------------===// // Div utility functions // - SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, + SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const; SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, std::vector<SDNode*> *Created) const; diff --git a/include/llvm/Target/TargetSelectionDAGInfo.h b/include/llvm/Target/TargetSelectionDAGInfo.h index 96793bc036..fe2fba42dc 100644 --- a/include/llvm/Target/TargetSelectionDAGInfo.h +++ b/include/llvm/Target/TargetSelectionDAGInfo.h @@ -54,7 +54,7 @@ public: /// for another call). If the target chooses to decline an AlwaysInline /// request here, legalize will resort to using simple loads and stores. virtual SDValue - EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, + EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, @@ -71,7 +71,7 @@ public: /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl, + EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, @@ -87,7 +87,7 @@ public: /// SDValue if the target declines to use custom code and a different /// lowering strategy should be used. virtual SDValue - EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, + EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, |