More renamings of Target/Machine*Info to Target/Target*Info

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5204 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 33 insertions, 48 deletions

diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index f7db820e6a..b4d5daa41c 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -12,8 +12,8 @@
 
 class MachineInstrInfo;
 class MachineInstrDescriptor;
-class MachineSchedInfo;
-class MachineRegInfo;
+class TargetSchedInfo;
+class TargetRegInfo;
 class TargetFrameInfo;
 class TargetCacheInfo;
 class TargetOptInfo;
@@ -57,8 +57,8 @@ public:
   // -- Machine-level optimization information (peephole only)
   // 
   virtual const MachineInstrInfo&       getInstrInfo() const = 0;
-  virtual const MachineSchedInfo&       getSchedInfo() const = 0;
-  virtual const MachineRegInfo&	        getRegInfo()   const = 0;
+  virtual const TargetSchedInfo&        getSchedInfo() const = 0;
+  virtual const TargetRegInfo&          getRegInfo()   const = 0;
   virtual const TargetFrameInfo&        getFrameInfo() const = 0;
   virtual const TargetCacheInfo&        getCacheInfo() const = 0;
   virtual const TargetOptInfo&          getOptInfo()   const = 0;
diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h
index ff261827eb..2c82c48ca2 100644
--- a/include/llvm/Target/TargetRegInfo.h
+++ b/include/llvm/Target/TargetRegInfo.h
@@ -1,12 +1,12 @@
-//===-- llvm/Target/RegInfo.h - Target Register Information ------*- C++ -*-==//
+//===-- llvm/Target/TargetRegInfo.h - Target Register Info -------*- C++ -*-==//
 //
 // This file is used to describe the register system of a target to the
 // register allocator.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TARGET_MACHINEREGINFO_H
-#define LLVM_TARGET_MACHINEREGINFO_H
+#ifndef LLVM_TARGET_TARGETREGINFO_H
+#define LLVM_TARGET_TARGETREGINFO_H
 
 #include "Support/NonCopyable.h"
 #include "Support/hash_map"
@@ -24,17 +24,11 @@ class MachineInstr;
 class PhyRegAlloc;
 class BasicBlock;
 
-//-----------------------------------------------------------------------------
-// class MachineRegClassInfo
-// 
-// Purpose:
-//   Interface to description of machine register class (e.g., int reg class
-//   float reg class etc)
-// 
-//--------------------------------------------------------------------------
-
-
-class MachineRegClassInfo {
+///----------------------------------------------------------------------------
+///   Interface to description of machine register class (e.g., int reg class
+///   float reg class etc)
+///
+class TargetRegClassInfo {
 protected:
   const unsigned RegClassID;        // integer ID of a reg class
   const unsigned NumOfAvailRegs;    // # of avail for coloring -without SP etc.
@@ -51,31 +45,26 @@ public:
                            std::vector<bool> &IsColorUsedArr) const = 0;
   virtual bool isRegVolatile(int Reg) const = 0;
 
-  MachineRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR)
+  TargetRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR)
     : RegClassID(ID), NumOfAvailRegs(NVR), NumOfAllRegs(NAR) {}
 };
 
 
 
 //---------------------------------------------------------------------------
-// class MachineRegInfo
-// 
-// Purpose:
-//   Interface to register info of target machine
-// 
-//--------------------------------------------------------------------------
-
-class MachineRegInfo : public NonCopyableV {
+/// TargetRegInfo - Interface to register info of target machine
+///
+class TargetRegInfo : public NonCopyableV {
 protected:
   // A vector of all machine register classes
   //
-  std::vector<const MachineRegClassInfo *> MachineRegClassArr;    
+  std::vector<const TargetRegClassInfo *> MachineRegClassArr;    
   
 public:
   const TargetMachine &target;
 
-  MachineRegInfo(const TargetMachine& tgt) : target(tgt) { }
-  ~MachineRegInfo() {
+  TargetRegInfo(const TargetMachine& tgt) : target(tgt) { }
+  ~TargetRegInfo() {
     for (unsigned i = 0, e = MachineRegClassArr.size(); i != e; ++i)
       delete MachineRegClassArr[i];
   }
@@ -96,7 +85,7 @@ public:
     return MachineRegClassArr.size(); 
   }  
 
-  const MachineRegClassInfo *getMachineRegClass(unsigned i) const { 
+  const TargetRegClassInfo *getMachineRegClass(unsigned i) const { 
     return MachineRegClassArr[i]; 
   }
 
@@ -136,7 +125,7 @@ public:
 
 
   // The following methods are used to generate "copy" machine instructions
-  // for an architecture. Currently they are used in MachineRegClass 
+  // for an architecture. Currently they are used in TargetRegClass 
   // interface. However, they can be moved to MachineInstrInfo interface if
   // necessary.
   //
diff --git a/include/llvm/Target/TargetSchedInfo.h b/include/llvm/Target/TargetSchedInfo.h
index 293835cefa..e45dddf623 100644
--- a/include/llvm/Target/TargetSchedInfo.h
+++ b/include/llvm/Target/TargetSchedInfo.h
@@ -1,11 +1,11 @@
-//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==//
+//===- Target/TargetSchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
 //
 // This file describes the target machine to the instruction scheduler.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
-#define LLVM_TARGET_MACHINESCHEDINFO_H
+#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
+#define LLVM_TARGET_TARGETSCHEDINFO_H
 
 #include "llvm/Target/MachineInstrInfo.h"
 #include "Support/hash_map"
@@ -164,19 +164,15 @@ private:
     feasibleSlots.resize(maxNumSlots);
   }
   
-  friend class MachineSchedInfo;	// give access to these functions
+  friend class TargetSchedInfo;	// give access to these functions
 };
 
 
 //---------------------------------------------------------------------------
-// class MachineSchedInfo
-//
-// Purpose:
-//   Common interface to machine information for instruction scheduling
-//---------------------------------------------------------------------------
-
-class MachineSchedInfo {
-public:
+/// TargetSchedInfo - Common interface to machine information for 
+/// instruction scheduling
+///
+struct TargetSchedInfo {
   const TargetMachine& target;
   
   unsigned maxNumIssueTotal;
@@ -203,17 +199,17 @@ protected:
   }
 
 private:
-  MachineSchedInfo(const MachineSchedInfo &);  // DO NOT IMPLEMENT
-  void operator=(const MachineSchedInfo &);  // DO NOT IMPLEMENT
+  TargetSchedInfo(const TargetSchedInfo &);  // DO NOT IMPLEMENT
+  void operator=(const TargetSchedInfo &);  // DO NOT IMPLEMENT
 public:
-  /*ctor*/	   MachineSchedInfo	(const TargetMachine& tgt,
+  /*ctor*/	   TargetSchedInfo	(const TargetMachine& tgt,
                                          int                  _numSchedClasses,
 					 const InstrClassRUsage* _classRUsages,
 					 const InstrRUsageDelta* _usageDeltas,
 					 const InstrIssueDelta*  _issueDeltas,
 					 unsigned _numUsageDeltas,
 					 unsigned _numIssueDeltas);
-  /*dtor*/ virtual ~MachineSchedInfo	() {}
+  /*dtor*/ virtual ~TargetSchedInfo() {}
   
   inline const MachineInstrInfo& getInstrInfo() const {
     return *mii;