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| author | Jim Grosbach <grosbach@apple.com> | 2014-02-07 00:16:33 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2014-02-07 00:16:33 +0000 |
| commit | 1f65cfad962a2f0c27b2dcc2324a76c427ba7e2b (patch) | |
| tree | d8131ef94f0732551a7aa8fd804736166066b49b /include/llvm | |
| parent | 1dd4d5f760602de5a1f26abf2d4e6d67007696ad (diff) | |
| download | llvm-1f65cfad962a2f0c27b2dcc2324a76c427ba7e2b.tar.gz llvm-1f65cfad962a2f0c27b2dcc2324a76c427ba7e2b.tar.bz2 llvm-1f65cfad962a2f0c27b2dcc2324a76c427ba7e2b.tar.xz | |
X86: Resolve a long standing FIXME and properly isel pextr[bw].
Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use
them to match the relevant pextr store instructions.
The test widen_load-2.ll requires a slight change because with the
stores gone, the remaining instructions are scheduled in a different
order.
Add test cases for SSE4 and AVX variants.
Resolves rdar://13414672.
Patch by Adam Nemet <anemet@apple.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200957 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm')
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index d94bdc67bf..18ff04c079 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -492,6 +492,12 @@ def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", // Do not use cvt directly. Use cvt forms below def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; +def SDT_assertext : SDTypeProfile<1, 1, + [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; +def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>; +def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>; + + //===----------------------------------------------------------------------===// // Selection DAG Condition Codes |