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author | Tim Northover <tnorthover@apple.com> | 2014-02-10 14:04:07 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-02-10 14:04:07 +0000 |
commit | 9ed30bb2303dc4676af9892f780a14a019d030c6 (patch) | |
tree | a2c854b5dc79975549dcdbe0498d187458061488 /include/llvm | |
parent | 5a2ae984073242d922850d23c859cc0439b54401 (diff) | |
download | llvm-9ed30bb2303dc4676af9892f780a14a019d030c6.tar.gz llvm-9ed30bb2303dc4676af9892f780a14a019d030c6.tar.bz2 llvm-9ed30bb2303dc4676af9892f780a14a019d030c6.tar.xz |
ARM: use LLVM IR to represent the vshrn operation
vshrn is just the combination of a right shift and a truncate (and the limits
on the immediate value actually mean the signedness of the shift doesn't
matter). Using that representation allows us to get rid of an ARM-specific
intrinsic, share more code with AArch64 and hopefully get better code out of
the mid-end optimisers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201085 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm')
-rw-r--r-- | include/llvm/IR/IntrinsicsARM.td | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/llvm/IR/IntrinsicsARM.td b/include/llvm/IR/IntrinsicsARM.td index dd80e2e179..8002cc49b5 100644 --- a/include/llvm/IR/IntrinsicsARM.td +++ b/include/llvm/IR/IntrinsicsARM.td @@ -289,7 +289,6 @@ def int_arm_neon_vshifts : Neon_2Arg_Intrinsic; def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic; def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic; def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic; -def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic; // Vector Rounding Shift. def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic; |