Clarify the doxygen comment for AsmPrinter::EmitDwarfRegOpPiece and add

default arguments to the function.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207372 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 3 deletions

diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h
index f40f3337c7..51eeb0fb77 100644
--- a/include/llvm/CodeGen/AsmPrinter.h
+++ b/include/llvm/CodeGen/AsmPrinter.h
@@ -430,14 +430,21 @@ namespace llvm {
     /// encoding specified.
     virtual unsigned getISAEncoding() { return 0; }
 
-    /// \brief Emit a partial dwarf register operation.
+    /// \brief Emit a partial DWARF register operation.
     /// \param MLoc             the register
     /// \param PieceSizeInBits  size and
     /// \param PieceOffsetBits  offset of the piece in bits, if this is one
     ///                         piece of an aggregate value.
+    ///
+    /// If size and offset is zero an operation for the entire
+    /// register is emitted: Some targets do not provide a DWARF
+    /// register number for every register.  If this is the case, this
+    /// function will attempt to emit a DWARF register by emitting a
+    /// piece of a super-register or by piecing together multiple
+    /// subregisters that alias the register.
     void EmitDwarfRegOpPiece(ByteStreamer &BS, const MachineLocation &MLoc,
-                             unsigned PieceSize,
-                             unsigned PieceOffset) const;
+                             unsigned PieceSize = 0,
+                             unsigned PieceOffset = 0) const;
 
     /// EmitDwarfRegOp - Emit dwarf register operation.
     /// \param Indirect   whether this is a register-indirect address