Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down

to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8

7 files changed, 106 insertions, 48 deletions

diff --git a/include/llvm/CodeGen/MachineModuleInfo.h b/include/llvm/CodeGen/MachineModuleInfo.h
index fa185c46d5..c138dbfb72 100644
--- a/include/llvm/CodeGen/MachineModuleInfo.h
+++ b/include/llvm/CodeGen/MachineModuleInfo.h
@@ -170,7 +170,8 @@ public:
 
   MachineModuleInfo();  // DUMMY CONSTRUCTOR, DO NOT CALL.
   // Real constructor.
-  MachineModuleInfo(const MCAsmInfo &MAI, const TargetAsmInfo *TAI);
+  MachineModuleInfo(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
+                    const TargetAsmInfo *TAI);
   ~MachineModuleInfo();
 
   bool doInitialization();
diff --git a/include/llvm/MC/MCContext.h b/include/llvm/MC/MCContext.h
index 43a9ce6cfa..cdaa21f074 100644
--- a/include/llvm/MC/MCContext.h
+++ b/include/llvm/MC/MCContext.h
@@ -26,6 +26,7 @@ namespace llvm {
   class MCLabel;
   class MCDwarfFile;
   class MCDwarfLoc;
+  class MCRegisterInfo;
   class MCLineSection;
   class StringRef;
   class Twine;
@@ -46,6 +47,9 @@ namespace llvm {
     /// The MCAsmInfo for this target.
     const MCAsmInfo &MAI;
 
+    /// The MCRegisterInfo for this target.
+    const MCRegisterInfo &MRI;
+
     const TargetAsmInfo *TAI;
 
     /// Allocator - Allocator object used for creating machine code objects.
@@ -110,11 +114,14 @@ namespace llvm {
     MCSymbol *CreateSymbol(StringRef Name);
 
   public:
-    explicit MCContext(const MCAsmInfo &MAI, const TargetAsmInfo *TAI);
+    explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
+                       const TargetAsmInfo *TAI);
     ~MCContext();
 
     const MCAsmInfo &getAsmInfo() const { return MAI; }
 
+    const MCRegisterInfo &getRegisterInfo() const { return MRI; }
+
     const TargetAsmInfo &getTargetAsmInfo() const { return *TAI; }
 
     void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value; }
diff --git a/include/llvm/MC/MCRegisterInfo.h b/include/llvm/MC/MCRegisterInfo.h
index caf98bb89f..64f9fb4f10 100644
--- a/include/llvm/MC/MCRegisterInfo.h
+++ b/include/llvm/MC/MCRegisterInfo.h
@@ -16,6 +16,7 @@
 #ifndef LLVM_MC_MCREGISTERINFO_H
 #define LLVM_MC_MCREGISTERINFO_H
 
+#include "llvm/ADT/DenseMap.h"
 #include <cassert>
 
 namespace llvm {
@@ -51,17 +52,59 @@ struct MCRegisterDesc {
 ///
 class MCRegisterInfo {
 private:
-  const MCRegisterDesc *Desc;             // Pointer to the descriptor array
-  unsigned NumRegs;                       // Number of entries in the array
+  const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+  unsigned NumRegs;                           // Number of entries in the array
+  unsigned RAReg;                             // Return address register
+  DenseMap<unsigned, int> L2DwarfRegs;        // LLVM to Dwarf regs mapping
+  DenseMap<unsigned, int> EHL2DwarfRegs;      // LLVM to Dwarf regs mapping EH
+  DenseMap<unsigned, unsigned> Dwarf2LRegs;   // Dwarf to LLVM regs mapping
+  DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
+  DenseMap<unsigned, int> L2SEHRegs;          // LLVM to SEH regs mapping
 
 public:
   /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
   /// auto-generated routines. *DO NOT USE*.
-  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR) {
+  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA) {
     Desc = D;
     NumRegs = NR;
+    RAReg = RA;
+  }
+
+  /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
+  /// register number mapping. Called by TableGen auto-generated routines.
+  /// *DO NOT USE*.
+  void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
+    if (isEH)
+      EHL2DwarfRegs[LLVMReg] = DwarfReg;
+    else
+      L2DwarfRegs[LLVMReg] = DwarfReg;
   }
     
+  /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
+  /// register number mapping. Called by TableGen auto-generated routines.
+  /// *DO NOT USE*.
+  void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
+    if (isEH)
+      EHDwarf2LRegs[DwarfReg] = LLVMReg;
+    else
+      Dwarf2LRegs[DwarfReg] = LLVMReg;
+  }
+     
+  /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
+  /// number mapping. By default the SEH register number is just the same
+  /// as the LLVM register number.
+  /// FIXME: TableGen these numbers. Currently this requires target specific
+  /// initialization code.
+  void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
+    L2SEHRegs[LLVMReg] = SEHReg;
+  }
+
+  /// getRARegister - This method should return the register where the return
+  /// address can be found.
+  unsigned getRARegister() const {
+    return RAReg;
+  }
+
   const MCRegisterDesc &operator[](unsigned RegNo) const {
     assert(RegNo < NumRegs &&
            "Attempting to access record for invalid register number!");
@@ -122,6 +165,37 @@ public:
   unsigned getNumRegs() const {
     return NumRegs;
   }
+
+  /// getDwarfRegNum - Map a target register to an equivalent dwarf register
+  /// number.  Returns -1 if there is no equivalent value.  The second
+  /// parameter allows targets to use different numberings for EH info and
+  /// debugging info.
+  int getDwarfRegNum(unsigned RegNum, bool isEH) const {
+    const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
+    const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
+    if (I == M.end()) return -1;
+    return I->second;
+  }
+
+  /// getLLVMRegNum - Map a dwarf register back to a target register.
+  ///
+  int getLLVMRegNum(unsigned RegNum, bool isEH) const {
+    const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
+    const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
+    if (I == M.end()) {
+      assert(0 && "Invalid RegNum");
+      return -1;
+    }
+    return I->second;
+  }
+
+  /// getSEHRegNum - Map a target register to an equivalent SEH register
+  /// number.  Returns LLVM register number if there is no equivalent value.
+  int getSEHRegNum(unsigned RegNum) const {
+    const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
+    if (I == L2SEHRegs.end()) return (int)RegNum;
+    return I->second;
+  }
 };
  
 } // End llvm namespace
diff --git a/include/llvm/Target/TargetAsmInfo.h b/include/llvm/Target/TargetAsmInfo.h
index 5a526dcebc..f1ffbd51d4 100644
--- a/include/llvm/Target/TargetAsmInfo.h
+++ b/include/llvm/Target/TargetAsmInfo.h
@@ -29,7 +29,6 @@ namespace llvm {
 
 class TargetAsmInfo {
   std::vector<MachineMove> InitialFrameState;
-  const TargetRegisterInfo *TRI;
   const TargetFrameLowering *TFI;
   const TargetLoweringObjectFile *TLOF;
 
@@ -74,29 +73,9 @@ public:
     return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH);
   }
 
-  const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
-    return TRI->getCalleeSavedRegs(MF);
-  }
-
-  unsigned getDwarfRARegNum(bool isEH) const {
-    return TRI->getDwarfRegNum(TRI->getRARegister(), isEH);
-  }
-
   const std::vector<MachineMove> &getInitialFrameState() const {
     return InitialFrameState;
   }
-
-  int getDwarfRegNum(unsigned RegNum, bool isEH) const {
-    return TRI->getDwarfRegNum(RegNum, isEH);
-  }
-
-  int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
-    return TRI->getLLVMRegNum(DwarfRegNum, isEH);
-  }
-
-  int getSEHRegNum(unsigned RegNum) const {
-    return TRI->getSEHRegNum(RegNum);
-  }
 };
 
 }
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index b9d91f5f64..3113cd47f8 100644
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -699,28 +699,10 @@ public:
   //===--------------------------------------------------------------------===//
   /// Debug information queries.
 
-  /// getDwarfRegNum - Map a target register to an equivalent dwarf register
-  /// number.  Returns -1 if there is no equivalent value.  The second
-  /// parameter allows targets to use different numberings for EH info and
-  /// debugging info.
-  virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
-
-  virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0;
-
   /// getFrameRegister - This method should return the register used as a base
   /// for values allocated in the current stack frame.
   virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
 
-  /// getRARegister - This method should return the register where the return
-  /// address can be found.
-  virtual unsigned getRARegister() const = 0;
-
-  /// getSEHRegNum - Map a target register to an equivalent SEH register
-  /// number.  Returns -1 if there is no equivalent value.
-  virtual int getSEHRegNum(unsigned i) const {
-    return i;
-  }
-
   /// getCompactUnwindRegNum - This function maps the register to the number for
   /// compact unwind encoding. Return -1 if the register isn't valid.
   virtual int getCompactUnwindRegNum(unsigned, bool) const {
diff --git a/include/llvm/Target/TargetRegistry.h b/include/llvm/Target/TargetRegistry.h
index 7e0ce19f8f..a33d17ba57 100644
--- a/include/llvm/Target/TargetRegistry.h
+++ b/include/llvm/Target/TargetRegistry.h
@@ -69,7 +69,7 @@ namespace llvm {
     typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
                                             StringRef TT);
     typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
-    typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
+    typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
     typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
                                                         StringRef CPU,
                                                         StringRef Features);
@@ -263,10 +263,10 @@ namespace llvm {
 
     /// createMCRegInfo - Create a MCRegisterInfo implementation.
     ///
-    MCRegisterInfo *createMCRegInfo() const {
+    MCRegisterInfo *createMCRegInfo(StringRef Triple) const {
       if (!MCRegInfoCtorFn)
         return 0;
-      return MCRegInfoCtorFn();
+      return MCRegInfoCtorFn(Triple);
     }
 
     /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
@@ -803,7 +803,7 @@ namespace llvm {
       TargetRegistry::RegisterMCRegInfo(T, &Allocator);
     }
   private:
-    static MCRegisterInfo *Allocator() {
+    static MCRegisterInfo *Allocator(StringRef TT) {
       return new MCRegisterInfoImpl();
     }
   };
diff --git a/include/llvm/Target/TargetSelect.h b/include/llvm/Target/TargetSelect.h
index 272ee09464..3cccaa80b0 100644
--- a/include/llvm/Target/TargetSelect.h
+++ b/include/llvm/Target/TargetSelect.h
@@ -35,6 +35,10 @@ extern "C" {
 #include "llvm/Config/Targets.def"
 
 #define LLVM_TARGET(TargetName) \
+  void LLVMInitialize##TargetName##MCRegisterInfo();
+#include "llvm/Config/Targets.def"
+
+#define LLVM_TARGET(TargetName) \
   void LLVMInitialize##TargetName##MCSubtargetInfo();
 #include "llvm/Config/Targets.def"
 
@@ -98,6 +102,17 @@ namespace llvm {
 #include "llvm/Config/Targets.def"
   }
   
+  /// InitializeAllMCRegisterInfos - The main program should call this function
+  /// if it wants access to all available register infos for targets that
+  /// LLVM is configured to support, to make them available via the
+  /// TargetRegistry.
+  ///
+  /// It is legal for a client to make multiple calls to this function.
+  inline void InitializeAllMCRegisterInfos() {
+#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCRegisterInfo();
+#include "llvm/Config/Targets.def"
+  }
+  
   /// InitializeAllMCSubtargetInfos - The main program should call this function
   /// if it wants access to all available subtarget infos for targets that LLVM
   /// is configured to support, to make them available via the TargetRegistry.