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author | Owen Anderson <resistor@mac.com> | 2011-06-16 18:17:13 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2011-06-16 18:17:13 +0000 |
commit | 1300f3019e5d590231bbc3d907626708515d3212 (patch) | |
tree | 8841668d876a6bf2ddff54374637595982e87969 /include | |
parent | 43641a5d17e525f339d6cf51010a42a9479dc2a5 (diff) | |
download | llvm-1300f3019e5d590231bbc3d907626708515d3212.tar.gz llvm-1300f3019e5d590231bbc3d907626708515d3212.tar.bz2 llvm-1300f3019e5d590231bbc3d907626708515d3212.tar.xz |
Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133178 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetOpcodes.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h index 01fba6628e..37f7b2fb8d 100644 --- a/include/llvm/Target/TargetOpcodes.h +++ b/include/llvm/Target/TargetOpcodes.h @@ -71,6 +71,10 @@ namespace TargetOpcode { /// REG_SEQUENCE - This variadic instruction is used to form a register that /// represent a consecutive sequence of sub-registers. It's used as register /// coalescing / allocation aid and must be eliminated before code emission. + // In SDNode form, the first operand encodes the register class created by + // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index + // pair. Once it has been lowered to a MachineInstr, the regclass operand + // is no longer present. /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 /// After register coalescing references of v1024 should be replace with /// v1027:3, v1025 with v1027:4, etc. |