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author | Andrew Trick <atrick@apple.com> | 2012-07-02 18:10:42 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2012-07-02 18:10:42 +0000 |
commit | 218ee74a011c0d350099c452810da0bd57a15047 (patch) | |
tree | 58e25d935c68661cd1654a02633e20c3a5c2ea56 /include | |
parent | 7c3a65c7edceb3a013cf49d376c3bc016eb871bf (diff) | |
download | llvm-218ee74a011c0d350099c452810da0bd57a15047.tar.gz llvm-218ee74a011c0d350099c452810da0bd57a15047.tar.bz2 llvm-218ee74a011c0d350099c452810da0bd57a15047.tar.xz |
Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/MC/MCInstrItineraries.h | 3 | ||||
-rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 4 | ||||
-rw-r--r-- | include/llvm/Target/TargetSchedule.td | 19 |
3 files changed, 14 insertions, 12 deletions
diff --git a/include/llvm/MC/MCInstrItineraries.h b/include/llvm/MC/MCInstrItineraries.h index 1003fb586c..d8587068ae 100644 --- a/include/llvm/MC/MCInstrItineraries.h +++ b/include/llvm/MC/MCInstrItineraries.h @@ -95,7 +95,7 @@ struct InstrStage { /// operands are read and written. /// struct InstrItinerary { - unsigned NumMicroOps; ///< # of micro-ops, 0 means it's variable + int NumMicroOps; ///< # of micro-ops, -1 means it's variable unsigned FirstStage; ///< Index of first stage in itinerary unsigned LastStage; ///< Index of last + 1 stage in itinerary unsigned FirstOperandCycle; ///< Index of first operand rd/wr @@ -323,7 +323,6 @@ public: } }; - } // End llvm namespace #endif diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 9c73cbcf4c..f096946b38 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -651,7 +651,9 @@ public: } /// getNumMicroOps - Return the number of u-operations the given machine - /// instruction will be decoded to on the target cpu. + /// instruction will be decoded to on the target cpu. The itinerary's + /// IssueWidth is the number of microops that can be dispatched each + /// cycle. An instruction with zero microops takes no dispatch resources. virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const = 0; diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index e22e67cdac..caa5a84c83 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -73,20 +73,20 @@ class InstrStage<int cycles, list<FuncUnit> units, // across all chip sets. Thus a new chip set can be added without modifying // instruction information. // -// NumMicroOps represents the number of micro-operations that each instruction -// in the class are decoded to. If the number is zero, then it means the -// instruction can decode into variable number of micro-ops and it must be -// determined dynamically. -// -class InstrItinClass<int ops = 1> { - int NumMicroOps = ops; -} +class InstrItinClass; def NoItinerary : InstrItinClass; //===----------------------------------------------------------------------===// // Instruction itinerary data - These values provide a runtime map of an // instruction itinerary class (name) to its itinerary data. // +// NumMicroOps represents the number of micro-operations that each instruction +// in the class are decoded to. If the number is zero, then it means the +// instruction can decode into variable number of micro-ops and it must be +// determined dynamically. This directly relates to the itineraries +// global IssueWidth property, which constrains the number of microops +// that can issue per cycle. +// // OperandCycles are optional "cycle counts". They specify the cycle after // instruction issue the values which correspond to specific operand indices // are defined or read. Bypasses are optional "pipeline forwarding pathes", if @@ -106,8 +106,9 @@ def NoItinerary : InstrItinClass; // is reduced by 1. class InstrItinData<InstrItinClass Class, list<InstrStage> stages, list<int> operandcycles = [], - list<Bypass> bypasses = []> { + list<Bypass> bypasses = [], int uops = 1> { InstrItinClass TheClass = Class; + int NumMicroOps = uops; list<InstrStage> Stages = stages; list<int> OperandCycles = operandcycles; list<Bypass> Bypasses = bypasses; |