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authorAnand Shukla <ashukla@cs.uiuc.edu>2002-07-11 00:16:28 +0000
committerAnand Shukla <ashukla@cs.uiuc.edu>2002-07-11 00:16:28 +0000
commit24787fa2ed43dc58813b14ac18fbc402a7315062 (patch)
treee8d05f944462cd4566626e7bddad1717fadf0372 /include
parent4c7b04508ef0069cbd0935aab5d69272a8675cc8 (diff)
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added std:: to vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2874 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/Target/TargetRegInfo.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h
index 33bcf15e58..7ec5ee26b0 100644
--- a/include/llvm/Target/TargetRegInfo.h
+++ b/include/llvm/Target/TargetRegInfo.h
@@ -220,8 +220,8 @@ public:
// an architecture. This must insert code for saving and restoring
// such registers on
//
- virtual void insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
- vector<MachineInstr*>& instrnsAfter,
+ virtual void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
+ std::vector<MachineInstr*>& instrnsAfter,
MachineInstr *MInst,
const BasicBlock *BB,
PhyRegAlloc &PRA) const = 0;