summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorChris Lattner <sabre@nondot.org>2002-10-28 04:30:20 +0000
committerChris Lattner <sabre@nondot.org>2002-10-28 04:30:20 +0000
commit6d6c3f86186333037f2fd3fb001e8b2998c080d9 (patch)
tree0c9307b9224aac7fa26b179f82fc61c7d4a7ad96 /include
parent572f5c8c0cf66cd6f53dda255cd8c4d8f27d8505 (diff)
downloadllvm-6d6c3f86186333037f2fd3fb001e8b2998c080d9.tar.gz
llvm-6d6c3f86186333037f2fd3fb001e8b2998c080d9.tar.bz2
llvm-6d6c3f86186333037f2fd3fb001e8b2998c080d9.tar.xz
Add new getOperandType(i) method to MachineInstr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4330 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/CodeGen/MachineInstr.h28
1 files changed, 16 insertions, 12 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 0b5ceaf272..ba901a8d74 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -238,14 +238,6 @@ public:
//
unsigned getNumOperands() const { return operands.size(); }
- bool operandIsDefined(unsigned i) const {
- return getOperand(i).opIsDef();
- }
-
- bool operandIsDefinedAndUsed(unsigned i) const {
- return getOperand(i).opIsDefAndUse();
- }
-
const MachineOperand& getOperand(unsigned i) const {
assert(i < operands.size() && "getOperand() out of range!");
return operands[i];
@@ -254,6 +246,18 @@ public:
assert(i < operands.size() && "getOperand() out of range!");
return operands[i];
}
+
+ MachineOperand::MachineOperandType getOperandType(unsigned i) const {
+ return getOperand(i).getOperandType();
+ }
+
+ bool operandIsDefined(unsigned i) const {
+ return getOperand(i).opIsDef();
+ }
+
+ bool operandIsDefinedAndUsed(unsigned i) const {
+ return getOperand(i).opIsDefAndUse();
+ }
//
// Information about implicit operands of the instruction
@@ -339,7 +343,7 @@ public:
// physical register after register allocation is complete.
//
void SetRegForOperand(unsigned i, int regNum);
-
+
//
// Iterator to enumerate machine operands.
//
@@ -348,10 +352,10 @@ public:
unsigned i;
MITy MI;
- inline void skipToNextVal() {
+ void skipToNextVal() {
while (i < MI->getNumOperands() &&
- !((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
- MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
+ !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
+ MI->getOperandType(i) == MachineOperand::MO_CCRegister)
&& MI->getOperand(i).getVRegValue() != 0))
++i;
}