diff options
author | Chandler Carruth <chandlerc@gmail.com> | 2014-04-21 07:11:15 +0000 |
---|---|---|
committer | Chandler Carruth <chandlerc@gmail.com> | 2014-04-21 07:11:15 +0000 |
commit | 81549a0a3907f7e49f4f49bdfdadc313cf61025a (patch) | |
tree | 18e6fe174a3449ce55dd4a40c2b1bcefa1948c2c /include | |
parent | 215fc7d9988bda6ae21370def427aaa81349a34a (diff) | |
download | llvm-81549a0a3907f7e49f4f49bdfdadc313cf61025a.tar.gz llvm-81549a0a3907f7e49f4f49bdfdadc313cf61025a.tar.bz2 llvm-81549a0a3907f7e49f4f49bdfdadc313cf61025a.tar.xz |
Revert r206732 which is causing llc to crash on most of the build bots.
Original commit message:
Implement builtins for safe division: safe.sdiv.iN, safe.udiv.iN,
safe.srem.iN, safe.urem.iN (iN = i8, i61, i32, or i64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206735 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/IR/Intrinsics.td | 13 | ||||
-rw-r--r-- | include/llvm/Target/TargetLowering.h | 16 |
2 files changed, 0 insertions, 29 deletions
diff --git a/include/llvm/IR/Intrinsics.td b/include/llvm/IR/Intrinsics.td index c65b86f5b7..6a48f17393 100644 --- a/include/llvm/IR/Intrinsics.td +++ b/include/llvm/IR/Intrinsics.td @@ -444,19 +444,6 @@ def int_umul_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; -def int_safe_udiv : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], - [LLVMMatchType<0>, LLVMMatchType<0>], - [IntrNoMem]>; -def int_safe_urem : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], - [LLVMMatchType<0>, LLVMMatchType<0>], - [IntrNoMem]>; -def int_safe_sdiv : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], - [LLVMMatchType<0>, LLVMMatchType<0>], - [IntrNoMem]>; -def int_safe_srem : Intrinsic<[llvm_anyint_ty, llvm_i1_ty], - [LLVMMatchType<0>, LLVMMatchType<0>], - [IntrNoMem]>; - //===------------------------- Memory Use Markers -------------------------===// // def int_lifetime_start : Intrinsic<[], diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 2e4956f16d..5afcd80a28 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -218,10 +218,6 @@ public: /// Return true if pow2 div is cheaper than a chain of srl/add/sra. bool isPow2DivCheap() const { return Pow2DivIsCheap; } - /// Return true if Div never traps, returns 0 when div by 0 and return TMin, - /// when sdiv TMin by -1. - bool isDivWellDefined() const { return DivIsWellDefined; } - /// Return true if Flow Control is an expensive operation that should be /// avoided. bool isJumpExpensive() const { return JumpIsExpensive; } @@ -1030,13 +1026,6 @@ protected: /// signed divide by power of two, and let the target handle it. void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; } - /// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem - /// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is - /// SignedMinValue and RHS is -1. - void setDivIsWellDefined (bool isWellDefined = true) { - DivIsWellDefined = isWellDefined; - } - /// Add the specified register class as an available regclass for the /// specified value type. This indicates the selector can handle values of /// that class natively. @@ -1452,11 +1441,6 @@ private: /// signed divide by power of two, and let the target handle it. bool Pow2DivIsCheap; - /// Tells the code-generator that it is safe to execute sdiv/udiv/srem/urem - /// even when RHS is 0. It is also safe to execute sdiv/srem when LHS is - /// SignedMinValue and RHS is -1. - bool DivIsWellDefined; - /// Tells the code generator that it shouldn't generate extra flow control /// instructions and should attempt to combine flow control instructions via /// predication. |