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authorEli Friedman <eli.friedman@gmail.com>2011-09-07 02:23:42 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-09-07 02:23:42 +0000
commit981a010c095b8fb57422df6fb90b6d802082afc5 (patch)
tree144379b0acab29ba55ce76e76a3b593d0c294265 /include
parent08708c8ef3185058ef879a977f580996b83b75ea (diff)
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Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139221 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 2ecdc9a48c..6c7be69b4d 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -998,8 +998,10 @@ class AtomicSDNode : public MemSDNode {
assert(getOrdering() == Ordering && "Ordering encoding error!");
assert(getSynchScope() == SynchScope && "Synch-scope encoding error!");
- assert(readMem() && "Atomic MachineMemOperand is not a load!");
- assert(writeMem() && "Atomic MachineMemOperand is not a store!");
+ assert((readMem() || getOrdering() <= Monotonic) &&
+ "Acquire/Release MachineMemOperand must be a load!");
+ assert((writeMem() || getOrdering() <= Monotonic) &&
+ "Acquire/Release MachineMemOperand must be a store!");
}
public: