diff options
| author | Dan Gohman <gohman@apple.com> | 2012-05-11 00:19:32 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2012-05-11 00:19:32 +0000 |
| commit | d4347e1af9141ec9f8e3e527367bfd16c0cc4ffb (patch) | |
| tree | 15339f77ace4f0f4501e61e22ce6d01f82bce24a /include | |
| parent | 61aef8bdf7a60bb1ab510fee0c5b2792468aadd3 (diff) | |
| download | llvm-d4347e1af9141ec9f8e3e527367bfd16c0cc4ffb.tar.gz llvm-d4347e1af9141ec9f8e3e527367bfd16c0cc4ffb.tar.bz2 llvm-d4347e1af9141ec9f8e3e527367bfd16c0cc4ffb.tar.xz | |
Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),
but it generates int3 on x86 instead of ud2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
| -rw-r--r-- | include/llvm/CodeGen/ISDOpcodes.h | 3 | ||||
| -rw-r--r-- | include/llvm/Intrinsics.td | 2 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 2 |
3 files changed, 7 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index ab8ab5dd7b..e570e12503 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -582,6 +582,9 @@ namespace ISD { // TRAP - Trapping instruction TRAP, + // DEBUGGER - Trap intented to get the attention of a debugger. + DEBUGGER, + // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are // their first operand. The other operands are the address to prefetch, // read / write specifier, locality specifier and instruction / data cache diff --git a/include/llvm/Intrinsics.td b/include/llvm/Intrinsics.td index f5883b6bdf..6b09cbd785 100644 --- a/include/llvm/Intrinsics.td +++ b/include/llvm/Intrinsics.td @@ -399,6 +399,8 @@ def int_flt_rounds : Intrinsic<[llvm_i32_ty]>, GCCBuiltin<"__builtin_flt_rounds">; def int_trap : Intrinsic<[]>, GCCBuiltin<"__builtin_trap">; +def int_debugger : Intrinsic<[]>, + GCCBuiltin<"__builtin_debugger">; // Intrisics to support half precision floating point format let Properties = [IntrNoMem] in { diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index f55cf0e630..361b42a12b 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -404,6 +404,8 @@ def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; def trap : SDNode<"ISD::TRAP" , SDTNone, [SDNPHasChain, SDNPSideEffect]>; +def debugger : SDNode<"ISD::DEBUGGER" , SDTNone, + [SDNPHasChain, SDNPSideEffect]>; def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, |